Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-04
2006-07-04
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S033000
Reexamination Certificate
active
07073107
ABSTRACT:
A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information. The integrated circuits within each of the bins are tested with a second test at a second level of testing at a succeeding testing step in the fabrication cycle of the integrated circuits to produce second test results associated with a second characteristic of the integrated circuits. The second characteristic is related to the first characteristic and the second level of testing is varied from bin to bin based at least in part on the defectivity value for the bin being tested.
REFERENCES:
patent: 5068814 (1991-11-01), Stark et al.
patent: 5726920 (1998-03-01), Chen et al.
patent: 6167545 (2000-12-01), Statovici et al.
patent: 6175812 (2001-01-01), Boyington et al.
patent: 6304095 (2001-10-01), Miyamoto
patent: 6618682 (2003-09-01), Bulaga et al.
patent: 6943575 (2005-09-01), Marr
patent: 6966019 (2005-11-01), Viens et al.
patent: 2002/0121915 (2002-09-01), Alonso Montull et al.
patent: 2003/0151422 (2003-08-01), Barnett et al.
Van der Pol et al., “Impact of Screening of Latent Defects at Electrical Test on the Yield-Reliability Relation and Application to Burn-in Elimination”, Mar. 31-Apr. 2, 1998, 1998 IEEE International Proceedings, pp. 370-377.
S. Brenner, “Optimal Production Test Times Through Adaptive Test Programming”, Oct. 30-Nov. 1, 2001, ITC International Test Conference, pp. 908-915.
Butler et al., “An Emperical Study on the Effects of Test Type Ordering on Overall Test Efficiency”, Oct. 3-5, 2000, ITC International Test Conference, pp. 408-416.
Daasch et al., “Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data”, Oct. 30-Nov. 1, 2001, ITC International Test Conference, pp. 92-100.
Miller et al., “Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort”, Oct. 30-Nov. 1, 2001, ITC Proceedings, 2001, pp. 1118-1127.
Madge Robert
Rajagopalan Vijayashanker
Lamarre Guy
LSI Logic Corporation
Luedeka Neely & Graham PC
Trimmings John P.
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