Input buffer circuit with hysteresis for noise control

Details Input buffer circuit with hysteresis for noise control Input buffer circuit with hysteresis for noise control

1996-07-23

1998-08-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327 53, 327 54, 327391, 326 34, 323316, H03K 3297, H03K 19094, H03K 1716

Patent

active

057962812

ABSTRACT:
In an interface for an input signal with a small amplitude and a high bit rate, the output voltage of a receiver can become more indeterminate when the input signal voltage at the receiving end of a signal transmission line becomes equal to a reference voltage V.sub.ref. In the input buffer circuit of the CMOS current mirror type, a transistor Q.sub.2 is connected in parallel with another transistor Q.sub.1, where the conductivity types of both the transistors are the same and a reference voltage V.sub.ref is applied to the gate electrode of the transistor Q.sub.1. The transistor Q.sub.2 endows the input buffer circuit with a hysteresis characteristic, and the output power N1 of the input buffer circuit is supplied to the gate electrode of the transistor Q.sub.2.

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Gunning, et al., "A CMOS Low Voltage-Swing Transmission-Line Transceiver", ISSCC Digest of Technical Papers, 1992, pp. 58-59.

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