Simultaneous resynchronization by command for state machines...
Simultaneous writing and reconstruction of a redundant array...
Simultaneously multithreaded processing and single event...
Simultaneously multithreaded processing and single event...
Single chip processor with externally executed test function
Single I/O session to commit a single transaction
Single platform electronic tester
Single point of entry/origination item scanning within an...
Single step debug card using the PCI interface
Single-chip memory system having a redundancy judging circuit
Single-processor system
SIP server architecture fault tolerance and failover
SIP server architecture for improving latency during message...
Situational aware output configuration and execution
Situational aware output configuration and execution
Sliding window mechanism for data capture and failure analysis
Slow response in redundant arrays of inexpensive disks
Smart card for high-availability clustering
Smart card for high-availability clustering
Smart debug interface circuit