Single-chip memory system having a redundancy judging circuit

Details Single-chip memory system having a redundancy judging circuit Single-chip memory system having a redundancy judging circuit

1997-01-27

1999-09-14

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

G06F 1100

Patent

active

059516925

ABSTRACT:
To use both an array of main memory cells and an array of redundant memory cells efficiently during a block writing operation, a memory system for performing the block writing operation includes a bit line activator activating at least one bit line of bit lines of the array of main memory cells and at least one bit line of bit lines of the array of redundant memory cells simultaneously during the block writing operation.

REFERENCES:
patent: 4601019 (1986-07-01), Shah et al.
patent: 4608687 (1986-08-01), Dutton
patent: 5228046 (1993-07-01), Blake et al.
patent: 5402377 (1995-03-01), Ohhata et al.

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