Single step debug card using the PCI interface

Details Single step debug card using the PCI interface Single step debug card using the PCI interface

2001-03-14

2004-06-15

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S015000

Reexamination Certificate

active

06751754

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a single step debug card and, more particularly, to a single step debug card that utilizes the peripheral component interconnect (PCI) interface.
2. Related Art
FIG. 1
depicts a structural block diagram of a computer system commonly used nowadays. Obviously, the CPU
10
connects to a north bridge (NB, a chipset)
30
through a CPU bus
20
. Other than connecting to memory
40
(which can be SDRAM, EDORAM, etc), the NB
30
also connects to an AGP VGA card
60
through an AGP bus
50
. The NB
30
also connects to a south bridge (SB, also a chipset)
80
through a PCI bus
70
for transferring data and information. Other than connecting with the hard drive (HD)
90
, the CD-ROM
100
, the universal serial bus (USB)
110
, input devices (such as the mouse and keyboard)
120
for retrieving or inputting data, the SB
80
also connects to the basic input/output system (BIOS)
150
and the audio device (such as a sound blaster card)
160
through an XD bus
130
and an ISA bus
140
, respectively.
The conventional single step interruption debug card is applied to an industry standard architecture (ISA) bus for terminating the IOCHRDY signal of the ISA bus cycle and forcing it to be at the low voltage. The object is to elongate the bus cycle so as to inspect the related address and the state of the data line bus.
On the PCI bus, the access of the CPU to the conventional BIOS has to first transfer the access cycle from the PCI bus to the ISA bus through a PCI/ISA bridge. After the BIOS data is read out by ROM on the ISA bus, the data are sent from the ISA bus back to the PCI bus through the PCI/ISA bridge. Since the BIOS data access cycle on the PCI bus has to be responded through and by the PCI/ISA bridge, that is, the relevant PCI cycle control signals such as DEVSEL# and TRDY# have to be generated by the PCI/ISA bridge, it is impossible to suspend the bus cycle by simply keep the signals that terminate the PCI cycle (such as TRDY#) at the high voltage.
The debug cards for the PCI bus available on the market have to rely on the assistance of the ISA bus interruption debug cards so as to force the IOCHRDY signal that terminate the ISA bus cycle at the low voltage, thus elongating the lifetime of the bus cycle. Or alternatively, at the beginning of booting the computer, part of the BIOS data and address are latched into buffer memory and are read out later. This does not really suspend the bus cycle to perform the real-time inspection function.
SUMMARY OF THE INVENTION
For a normal PCI bus cycle, when the FRAME# signal changes from HIGH to LOW, it signals the start of a PCI bus cycle. At this moment, the one shown on the AD bus is the address that the PCI bus cycle wants to position while the one shown on the C/BE# bus is the command. Each device on the PCI bus cycle will perform decoding on the address and command to ensure that whether it is a target device of the PCI bus cycle. If so, then the DEVSEL# signal is sent out to notify the PCI host to perform subsequent data transmission actions. If the target device cannot successfully complete the read/write action, that is, it cannot respond the TRDY# signal, then it can send out a STOP# signal to notify the PCI host to retry one cycle.
The single step debug card for the PCI interface of the invention utilizes the above-mentioned retry function. After it latches the signals of the address, data, command and BE# of the PCI bus cycle that are subject to inspection and displays them through an LED, it forces the DEVSEL# signal to be at the low voltage in the next cycle so as to respond in advance the PCI bus cycle and to maintain the TRDY# signal at the high voltage, elongating this cycle. The signals of the previously latched address, data, command and BE# can thus be shown on the LED all the time for inspection through the single step debugging. Finally, a STOP# signal is sent out through a switch circuit to notify the PCI host to retry the cycle. When the STOP# signal finishes, the DEVSEL# signal is also raised to HIGH to notify the PCI host to finish the intercepted cycle. When the cycle performs a retry, the above steps are repeated in order to achieve the function of single step debugging.


REFERENCES:
patent: 5864688 (1999-01-01), Santos et al.
patent: 6247087 (2001-06-01), Riley et al.
patent: 6526525 (2003-02-01), Chang

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