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Task management for data accesses to multiple logical...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Task synchronization mechanism and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Technique for accessing memory in a data processing apparatus

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Technique for converting system signals from one address configu

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Technique for data cache synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Technique for data transfer

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Technique for efficiently transferring moderate amounts of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Technique for implementing a distributed lock in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Technique for improving processor performance

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Technique for maintaining coherency between shared-disk and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Technique for migrating data between storage devices for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Technique for recovering mirror consistency in cooperative...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Technique for reducing latency of inter-reference ordering using

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Technique for reducing memory latency during a memory request

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Technique for referencing distributed shared memory locally...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Technique for updating a content addressable memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Technique for updating a content addressable memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Technique for using memory attributes

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Technique to avoid cascaded hot spotting

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Technique to perform concurrent updates to a shared data...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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