Technique for reducing latency of inter-reference ordering using

Details Technique for reducing latency of inter-reference ordering using Technique for reducing latency of inter-reference ordering using

1997-10-24

2000-04-25

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711147, 711151, 711152, 712 10, G06F 1300, G06F 1200

Patent

active

060556056

ABSTRACT:
A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

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