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Level 2 smartcache architecture supporting simultaneous...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Library device and logical number allocating method therefor

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Library device, operating mode setting method therefor

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Library of hard disk drives with transparent emulating...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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LIFO type data storage device incorporating two random...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Lightweight coherency control protocol for clustered storage...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Lightweight coherency control protocol for clustered storage...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Lightweight coherency control protocol for clustered storage...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Limit algorithm using queue depth to control application...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Limited concurrent host access in a logical volume...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Limiting the number of dirty entries in a computer cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Line cache controller with lookahead

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Line fill techniques

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Line rate buffer using single ported memories for variable...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Line swapping scheme to reduce back invalidations in a snoop...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Linear combiner weight memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Linear object management for a range of flash memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linear object management for a range of flash memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linear space allocation mechanisms in data space

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linked-list early race resolution mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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