Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-26
2011-04-26
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S159000
Reexamination Certificate
active
07934060
ABSTRACT:
A lightweight coherency control protocol ensures consistency of data containers, such as a file, and associated data buffers stored on one or more volumes served by a plurality of nodes, e.g., storage systems, connected as a cluster. Each data buffer is associated with a current cache sequence number comprising a load generation value and an update count value. The load generation value is incremented every time an inode of a file is loaded into a memory of the storage system. Once the inode is loaded and its load generation value is set, then the appropriate buffer of a buffer tree for the file is loaded into the memory. The update count value is incremented each time the buffer is updated with a write request/operation. Therefore, each buffer loaded into memory is tagged with the load generation value and an update count from the time that buffer is loaded.
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Corbett Peter F.
Wagner Christopher
Cesari and McKenna LLP
NetApp, Inc.
Nguyen Than
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