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Multiple access for parallel turbo decoder

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate

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Multiple input two-level cache directory with mini-directory for

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent

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Multiple memory addressing using adjustable chip select

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent

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Multiple-core processor with support for multiple virtual...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate

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Multiprocessor system and method thereof

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate

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Multischeme memory management system for computer

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing extended or expanded memory
Patent

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Multisection memory bank system

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate

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Multisection memory bank system

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
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