Multiple access for parallel turbo decoder

Details Multiple access for parallel turbo decoder Multiple access for parallel turbo decoder

2007-06-04

2011-11-01

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S157000

Reexamination Certificate

active

08051239

ABSTRACT:
A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.

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