Slave station, master station, bus system and method for...
Smart card system for use with peripheral devices
Smart retry system that reduces wasted bus transactions...
Smart retry system that reduces wasted bus transactions...
Smart target mechanism for eliminating dual address cycles...
Soft injection rate control for buses or network-on-chip...
Soft injection rate control for buses or network-on-chip...
Software locking mechanism for locking shared resources in a dat
Software method to retry access to peripherals that can...
Source synchronous transfer scheme for a high speed memory...
Source triggered transaction blocking
Spanning tree with fast link-failure convergence
Spanning tree with fast link-failure convergence
Split computer architecture to separate user and processor...
Split filtering in multilayer systems
Split transaction bus system
SRAM bus architecture and interconnect to an FPGA
State machine based bus cycle completion checking in a bus bridg
Storage apparatus
Storage device for a multibus architecture