Split transaction bus system

Details Split transaction bus system Split transaction bus system

2002-03-21

2004-11-23

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S309000, C710S240000

Reexamination Certificate

active

06823410

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a split transaction bus system, in particular, to a split transaction bus system having an improved read response speed.
2. Description of the Prior Art
In an information processing system in which a bus is shared among a plurality of devices, an arbiter is generally provided to arbitrate among the plurality of devices each requesting a bus ownership. In the case of a legacy bus, a device serving as a master transmits a bus request to the arbiter, receives a bus grant from the arbiter, and then start using the bus to conduct a write or read to or from a slave device. When the bus requests from two or more devices compete each other, a priority device is selected according to a preset priority logic, and the bus grant is transmitted thereto. A typical priority logic used is a scheme in which the priority is fixed or round robin scheduling in which the priority is changed for every arbitration. The master device having received the bus ownership transmits a read or a write command to a slave device via the bus, and then data is read from the slave device or written to the slave device. The master device occupies the bus during the period between the transmission of the command and the completion of the read or write. In the case of read, in particular, the bus is not released during a time required for data access in the slave device. In the case where a processor serving as the master device sends the read request to a memory serving as the slave device, the data is likely to be one immediately needed by the processor for processing, so that, in one aspect, it is advantageous to wait for the read response while occupying the bus. In another aspect, however, since another master device cannot use the bus if the slave device needs a long access time, a problem arises in that the utilization ratio of the bus is reduced.
For improving the utilization ratio of the bus, a split transaction bus is known. The split transaction bus allows the slave device to request the bus ownership from the arbiter. When the bus request from the master device is the request for read, the master device receives the bus grant from the arbiter, issues the read command to the bus, and then releases once the bus. The slave device, which has received the read command, transmits the bus request to the arbiter when the data is ready for output after a lapse of the access time.
FIG. 1A
is, an operation timing chart for a conventional split transaction bus. Two master devices and two slave devices are connected to the split transaction bus, and the bus ownership is arbitrated by the arbiter. Assume that, at a time t
1
, a bus request REQ(M
1
) from a first master device and a bus request REQ(M
2
) from a second master device are simultaneously issued. The arbiter determines to give the bus grant to the first master device according to a priority logic. At a time t
2
, the first master device receives the bus grant GNT(M
1
). At a time t
3
, the first master device issues a read command RR for a first slave device to the bus. After issuing the read command RR, the first master device releases the bus ownership at a time t
4
. The arbiter transmits a bus grant GNT(M
2
) to the second master device, which continuously transmits the bus request REQ(M
2
) . At a time t
5
, the second master device issues a write command WR for the second slave device to the bus. The second master device starts transferring write data WD at a time t
6
, completes a write cycle at a time t
8
, and then releases the bus ownership.
After a lapse of 5 clock cycles, which is equivalent to the read access time for the read command RR from the first master device, the first slave device transmits a bus request REQ(S
1
) for the read response to the arbiter at a time t
9
. At a time t
10
, the arbiter transmits the bus grant GNT(S
1
) to the first slave device. At a time t
11
, the first slave device starts transferring the read data RD to the first master device via the bus.
As described above, since in the split transaction bus, the first master device having made the read request releases the bus after issuing the read command RR, the second master device can use the bus during the access time of the first slave device, and therefore, the utilization ratio of the bus is improved.
However, in the first conventional split transaction bus, read data acquisition by the master device may be significantly delayed when the bus request for the read response and the bus request for block write or burst write for write-transferring a plurality of pieces of data compete each other. This problem will be described with reference to the operation timing chart shown in FIG.
1
B. The operation from the time t
1
to t
8
is the same as that shown in FIG.
1
A. Assume that the second master device transmits the bus request REQ(M
2
) to the arbiter at a time t
9
, the bus request REQ(M
2
) competes with the bus request REQ(S
1
) for the read response from the first slave device, and the arbiter transmits the bus grant GNT(M
2
) to the second master device. In response to the bus grant, at a time t
11
, the second master device issues the write command WR to the second slave device, and then at a time t
12
, transfers the write data WD. Since the bus is occupied during the period from the time t
11
to t
13
, the start of transfer of the read data RD from the first slave device is delayed to a time t
14
.
A second conventional arbitration method for the split transaction bus having solved this problem is described in Japanese Patent Laid-Open No. 8-263428. In this second conventional method, the arbiter gives the bus ownership in response to the bus request by priority unless the bus is being used. According to this method, the time between the transmission of the bus request from the slave device and the output of the read data RD to the bus can be reduced. In the case where the second conventional method is applied, as shown in an operation timing chart of
FIG. 2
, the arbiter issues the bus grant GNT(S
1
) to the slave device at the time t
10
, so that transfer of the read data RD is started as the time t
11
. At the time t
13
after the transfer of the read data RD is completed, the bus grant GNT(M
2
) in response to the bus request REQ(M
2
) from the second master device is issued, and at a time t
14
, the second master device outputs the write command WR to the bus.
In this second conventional method also, however, when competition with the bus request from another master device occurs, the time period for transmitting the bus grant from the time t
10
to t
11
, that is, an arbitration cycle is required, and thus there is yet room for improvement.
As a technique of reducing an overhead required for switching the bus grant, a system based on,a legacy bus system and having a parking function of previously transmitting the bus grant to a particular master device added thereto is known. As for the parking, a bus system capable of designating a default owner, to which the bus ownership is given by default when no master device uses the bus, that is, the bus is in a free state (idle state), is described in Japanese Patent Laid-Open No. 11-25035. In addition, in Japanese Patent Laid-Open No. 2000-35943, there is described a technique of analyzing a predetermined number of the last transactions for the master devices to determine one using the bus most frequently as the master device to be parked.
In the legacy bus system, however, only the master devices can transmit the bus request and acquire the bus grant. Even in the case of the system having the parking function, such as techniques described in Japanese Patent Laid-Open Nos. 11-25035 and 2000-35943, the target of the parking is limited to the master devices. Therefore, although it is possible to indirectly improve the read response by applying these techniques to advance the issue of the read command from the master device, it is impossible to directly improve the read response from the slave device. In addition, e

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