Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-12-29
2010-06-08
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000, C714S738000, C714S733000, C714S724000, C714S726000, C714S727000, C714S728000, C714S732000, C714S734000, C714S736000, C714S030000
Reexamination Certificate
active
07734973
ABSTRACT:
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.
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Hiraide Takahisa
Yamanaka Hitoshi
Fujitsu Microelectronics Limited
Staas & Halsey , LLP
Trimmings John P
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