Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2007-07-10
2010-10-19
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S208000, C712S212000
Reexamination Certificate
active
07818542
ABSTRACT:
A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
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International Search Report and Written Opinion of the International Searching Authority mailed Oct. 8, 2008 for International Application No. PCT/US2008/008469 filed Jul. 10, 2008.
Lie Sean
Shen Gene W.
GLOBALFOUNDRIES Inc.
Li Aimee J
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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