Self-aligned STI SONOS

Details Self-aligned STI SONOS Self-aligned STI SONOS

2007-12-04

2007-12-04

Smith, Bradley K. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C257SE21545

Reexamination Certificate

active

11113509

ABSTRACT:
Methods300and350are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect300comprises forming310a multi-layer dielectric-charge trapping-dielectric stack420over a substrate408of the wafer402, for example, an ONO stack420, removing312the multi-layer dielectric-charge trapping-dielectric stack420in a periphery region406of the wafer402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack420in a core region404of the wafer402. The method300further comprises forming314a gate dielectric layer426over the periphery region406of the substrate408, forming316a first polysilicon layer428over the multi-layer dielectric-charge trapping-dielectric stack420in the core region402and the gate dielectric426in the periphery region406, then concurrently forming318an isolation trench438in the substrate408in the core region404and in the periphery region406. Thereafter, the isolation trenches are filled326with a dielectric material446, and a second polysilicon layer452that is formed332over the first polysilicon layer428and the filled trenches438, forming an self-aligned STI structure446. The method300avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.

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International Search Report, Int'l Application No. PCT/US2006/015759, Int'l Filing Date Apr. 24, 2006, 3 pgs.

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