Method of fabrication on a gate pattern of a non-volatile...

Details Method of fabrication on a gate pattern of a non-volatile... Method of fabrication on a gate pattern of a non-volatile...

2005-07-05

2005-07-05

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06913972

ABSTRACT:
A method for fabricating a non-volatile memory device is provided. The method for fabricating a non-volatile memory device includes the steps of: forming a gate pattern in which a first conductive layer is used as a floating gate, a second conductive layer is used as a control gate, the first conductive layer, a dielectric layer, and the second conductive layer are sequentially stacked on a semiconductor substrate; forming a polishing stopper on the gate pattern and the semiconductor substrate; forming an interlayer insulating layer on the polishing stopper; forming a common source line (CSL) by etching a portion of the interlayer insulating layer, and a portion of the polishing stopper, and depositing a conductive material to the etched portions; planarizing the common source line and the interlayer insulating layer until the surface of the polishing stopper is exposed; partially etching back the polishing stopper until the surface of the second conductive layer is exposed; and forming a silicide layer on the exposed second conductive layer and the common source line.

REFERENCES:
patent: 5355332 (1994-10-01), Endoh et al.
patent: 6018195 (2000-01-01), Takebuchi
patent: 6350654 (2002-02-01), Sheu et al.
patent: 6492674 (2002-12-01), Komori

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