Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-05-08
2004-11-23
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06823486
ABSTRACT:
BACKGROUND
The present invention relates to generating test patterns for digital circuits and in particular to generating test patterns for functional registered transfer level circuits by using an assignment decision diagram and a nine symbol algebra.
Test pattern generation for digital circuits which are sequential in nature is often difficult. Typically a large amount of computing time and resources are required to generate test patterns that target detection of stuck-at faults at the logic level, even for a moderately sized digital circuit. Design for testability (DFT) techniques have been proposed that reduce the complexity of the digital circuit by altering the circuit. However, although testability of the circuit increases, area overhead penalties, performance penalties, power overhead penalties or a combination thereof are often encountered. Hence, using DFT techniques is not always an option for easier generation of test patterns.
Furthermore, conventional test pattern generators often target the digital circuit at its logic level. At this level, it may be impossible to generate test patterns for large sequential circuits that provide adequate stuck-at fault coverage. Even if test patterns are generated with great difficulty, problems discovered at this level do not make the design process easier or reduce design turnaround time.
At the register transfer level (RTL), the problem size is reduced as the number of primitive elements in the digital circuit at this level is less than at the logic level. As a result, the test generation problem is simplified. Also, since the design process often starts at this level, discovery of errors can be easily fixed rather than at the logic level.
SUMMARY OF THE INVENTION
The present invention provides a test pattern generation system and method for register transfer level circuits.
In accordance with one aspect of the invention, test patterns are generated by generating an assignment decision diagram of the register transfer level digital circuit. From the assignment decision diagram, modules are identified and objectives are determined by using a nine-valued symbolic algebra. The objectives are justified and propagated by traversing the assignment decision diagram to obtain a test environment. Predetermined test vectors are propagated through the register transfer level digital circuit using the test environment obtained. In one aspect of the invention, the assignment decision diagram comprises a graph-like structure representing functional behavior of the register transfer level digital circuit and an approximate structural representation of the register transfer level digital circuit. In further aspects of the invention, pre-computed test vectors for one of the modules identified are applied to the test environment to obtain a system-level test set for the module identified and system-level test sets for each of the modules identified are concatenated to obtain a complete test set for the register transfer level digital circuit.
In another aspect of the invention, test patterns are generated by receiving a functional register transfer level circuit design of the digital circuit having a single clock line. A data structure from the circuit design received is generated and logic structures and blocks from the data structure are identified. Test objectives are justified from the inputs of the logic structures and blocks from primary inputs of the register transfer level digital circuit to identify justification paths. Test objectives are propagated from outputs of the logic structures and blocks to primary outputs of the register transfer level digital circuit to identify propagation paths. Predetermined test vectors are propagated through the digital circuit using the justification and propagation paths identified. In further aspects of the invention, pre-computed test vectors for one of the logic structures and blocks identified are applied to the justification and propagation paths to obtain a system-level test set for one of the logic structures and blocks identified and the system-level test sets for each of the logic structures and blocks identified are concatenated to obtain a complete test set for the register transfer level digital circuit.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.
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Christie Parker & Hale LLP
Dildine R. Stephen
Fujitsu Limited
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