Silicon nitride island formation for increased capacitance

Details Silicon nitride island formation for increased capacitance Silicon nitride island formation for increased capacitance

2002-11-14

2004-08-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S254000

Reexamination Certificate

active

06770526

ABSTRACT:

BACKGROUND OF THE INVENTION
Semiconductor devices are employed in various systems in a wide variety of applications. An important type of semiconductor device used as a memory is known as dynamic random access memory (“DRAM”). The DRAM is extensively used for memory in computers and other electronic devices. A basic DRAM cell may include a capacitor and a transistor each formed in a semiconductor substrate. The capacitor stores a charge to represent a data value. The transistor allows the data value to be refreshed, read from, or written to the capacitor.
FIG. 11
illustrates a conventional DRAM memory cell
200
including a capacitor
210
and a transistor
220
. The capacitor
210
includes a first electrode
212
and a second electrode
214
. The transistor
220
includes a source (or drain)
222
connected to the second electrode
214
. The transistor
220
also includes a drain (or source)
224
connected to a bit line
232
, as well as a gate
226
connected to a word line
230
. The data value may be refreshed, read from or written to the capacitor
210
by applying appropriate voltages to the bit line
232
and/or the word line
230
.
A series of DRAM memory cells is typically arranged in an array. More DRAM cells can be fit onto a chip by reducing the size of the capacitor and/or the transistor, thus resulting in greater memory capacity for the chip. One method of minimizing the size of a DRAM cell is to reduce the surface area of the device, which may be accomplished by vertically constructing the components, i.e., where a semiconductor device includes components formed in several layers. One method of performing vertical construction involves stacking layers of material that form the capacitor and/or the transistor on the surface of a semiconductor substrate. An alternative vertical construction method is to form components in a trench in the semiconductor substrate. For example, a dopant may be added to portion of the substrate surrounding the trench in order to form one of the electrodes, the “outer electrode,” of the capacitor. A dielectric film may then be deposited along the sidewalls of the trench. Then, polycrystalline silicon, or “polysilicon” (poly-Si) may be deposited on the dielectric film, acting as the second electrode, the “inner electrode” or “storage electrode,” of the capacitor. Further processing steps may then be performed in order to finish fabricating the capacitor and other components of the memory cell, e.g., a buried strap connection to the transistor or connections to the bit line or word line of the memory cell.
As the surface area of a memory cell is made smaller and higher DRAM density is achieved, the trench region in which capacitors are formed may be reduced. Thus, the size of the trench typically, but not always, decreases as the memory capacity of the DRAM chip increases. As the size of the DRAM memory cell decreases, the capacitance of the capacitor becomes a critical parameter that can affect memory cell operation. Specifically, the capacitance needs to remain above a certain level in order for the capacitor to store charge effectively. Signal margin and retention time of the memory cell are directly affected by the capacitor's storage ability. In particular, the capacitor may need to maintain a capacitance of at least 25 fF. If the capacitance falls significantly below this level, the charge of the capacitor may dissipate too rapidly and the data value stored by the memory cell may be lost. In order to avoid such a problem, the capacitance is preferably at least 30-35 fF.
Such a capacitance may be achieved through various techniques. In one technique, trenches may be formed relatively deep into the substrate (“deep trenches”), for example between 4-8 &mgr;m below the substrate surface. This will permit the total size of the trench to remain the same, or even increase, when compared to a shallower but wider trench. Deep trenches having a small surface area are typically said to have a high aspect ratio. The “aspect ratio” is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. For example, memory cells fabricated as part of a 256 Mbyte DRAM chip may include capacitor trenches having an aspect ratio of between 10:1 and 20:1. This means that the depth of the trench walls is between 10 and 20 times greater than the width of the trench opening. In higher density DRAM chips, such as chips of 1 Gbyte or more, a typical deep trench aspect ratio may be on the order of 40:1 to 60:1 or higher. In such high aspect ratio situations, the trenches are typically very narrow. The very narrow trenches impact not only the thickness of the fill material of the inner electrode of the capacitor, but also how the fill material is formed in the trench. Thus, in order to properly fabricate a high aspect ratio deep trench capacitor, unconventional materials or processes may be required, which can increase the time and cost of manufacturing.
An alternative technique for increasing the capacitance of the capacitor is to form a “bottle” trench. Typically, a bottle trench is fabricated by first etching a standard trench shape, e.g., a vertical trench, in the semiconductor substrate. Then, the bottle shape may be created by widening a bottom portion of the trench. This may be accomplished by etching or a similar process. The width of the bottle shape may be limited by various parameters or physical dimensions of the memory cell. Therefore, a bottle trench may not be feasible in some situations.
Another technique for increasing capacitance is to fabricate a storage electrode with a “grainy” surface. The grainy surface provides increased surface area and, hence, increased capacitance. Commonly, the grainy storage electrode will comprise a layer of doped poly-Si within a trench or in a stacked structure. A form of poly-Si having a grainy surface is hemispherical grain poly-Si (HSG). Annealing amorphous silicon in an ultra high vacuum condition forms HSG. One drawback of HSG is that in a trench capacitor design the granular structure is constrained by the dimensions of the trench sidewalls. Another drawback to the HSG process is the need for a selective HSG removal step from the collar portion of the DRAM cell. This is typically achieved using a top-down RIE process which suffers from poor recess control and therefore incomplete HSG removal. Remaining HSG grains can provide an electrical short between the buried plate and poly-Si fill, thus rendering the memory cell inoperable. Thus, HSG may be unsuitable for memory cell designs.
SUMMARY OF THE INVENTION
A need exists for improved capacitance in memory cells. A need also exists for methods of forming memory cells having improved capacitance. The present invention provides an capacitor structure having a sufficient capacitance by forming a micro-masking structure in the trench during fabrication.
In accordance with one aspect of the invention, a method of fabricating a semiconductor device is provided. A trench having sidewalls is formed in a semiconductor substrate. The method employs a micro-masking structure to increase the surface area of the sidewalls, which will in turn allow for more storage electrode material, hence a greater capacitance. First, the micro-masking structure is distributed along the sidewalls to expose some portions of the sidewalls while covering other portions of the sidewalls. Next, the exposed portions of the sidewalls are recessed to form a plurality of recesses, giving the sidewalls increased surface area. Finally, the micro-masking structure is removed.
Preferably, the micro-masking structure includes a mask and islands disposed over the mask. The mask may be grown on the sidewalls. The islands may be deposited using a CVD process. The CVD process is preferably an LPCVD process performed at a temperature of between 575° C. to 800° C. for between 1-30 minutes such that the islands are distributed across the mask.
In accordance with another aspect of the invention, a semiconductor device is provided including a semiconductor substrate an

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