Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-05-14
2004-08-24
Kim, Robert H (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S044000, C349S110000, C349S138000, C349S139000
Reexamination Certificate
active
06781651
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate for liquid crystal displays and a method for fabricating the same and, more particularly, to a TFT array substrate of good performance characteristics.
(b) Description of the Related Art
Generally, a liquid crystal display (LCD) is formed with two glass substrates, and a liquid crystal sandwiched in-between the substrates.
One of the substrates has a common electrode, a color filter and a black matrix, and the other substrate has pixel electrodes and thin film transistors (TFTs). The former substrate is usally called the “color filter substrate,” and the latter substrate called the “TFT array substrate.”
The TFT array substrate is fabricated through forming a plurality of thin films, and performing photolithography with respect to the thin films. In photolithograpy, a number of masks are used for uniformly etching the thin films, involving complicated processing steps and increased production cost. Therefore, reduction in the number of masks becomes a critical factor in the fabrication of the TFT array substrate.
On the other hand, the color filter substrate is provided with a black matrix. The black matrix should be formed with a predetermined degree of marginal width considering the possible alignment error when assembling the color filter substrate and the TFT array substrate. However, the wider black matrix reduces the opening ratio. Therefore, it is required to increase the opening ratio of the black matrix while maintaining other performance characteristics in a stable manner.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a TFT array substrate for a LCD which involves reduced number of masks while simplifying the processing steps.
It is another object of the present invention to provide a method for fabricating a TFT array substrate with an increased device opening ratio.
These and other objects may be achieved in the flollowing way.
A mesh-shaped black matrix is formed under the TFTs with opening portions at pixel areas. A gate insulating layer and a protective layer are etched at the step of forming a semiconductor pattern while forming contact holes for interconnecting conductive layers.
Specifically, a black matrix is formed on a first substrate while being mesh-shaped with opening portions at pixel areas. An insulating layer is formed on the substrate while covering the black matrix. A gate line assembly is formed on the insulating layer. The gate line assembly includes gate lines proceeding in the horizontal direction, and gate electrodes connected to the gate lines. A gate insulating layer, and a semiconductor layer are sequentially deposited onto the substrate. An ohmic contact layer is formed on the semiconductor layer, and a data line assembly is formed on the ohmic contact layer. The data line assembly includes source and drain electrodes separated from each other, and data lines connected to the source electrodes while crossing over the gate lines to define the pixel areas. A protective layer is deposited onto the substrate while covering the data line assembly and the gate line assembly. The protective layer, the gate insulating layer, and the semiconductor layer are patterned to thereby form opening portions exposing the insulating layer at the pixel areas.
Pixel electrodes are formed on the protective layer such that they are connected to the drain electrodes. First contact holes exposing the drain electrodes are formed at the step of forming the opening portioins, and the connection of the pixel electrodes to the drain electrodes is made through the first contact holes.
The black matrix is separated into a number of portions, and buffer layers are positioned between the neighboring separate portions of the black matrix. The buffer layers are placed at the same plane as the gate line assembly or the data line assembly.
Each pixel electrode has a peripheral portion overlapped with the black matrix. The protective layer is formed in the same shape as the gate insulating pattern and the semiconductor pattern except the first contact holes. The borderlines of the protective layer, the gate insulating pattern, and the semiconductor pattern are placed over the black matrix except the area where the drain electrodes are present.
The gate line assembly further includes gate pads connected to the gate lines to receive scanning signals from the outside and transmit the scanning signals to the gate lines. The gate insultaing pattern, the semiconductor pattern and the protective layer have second contact holes exposing the gate pads.
The data line assembly further includes data pads connected to the data lines to receive picture signals from the outside and transmit the picture signals to the data lines. The gate insultaing pattern, the semiconductor pattern and the protective layer have third contact holes exposing the data pads.
Subsidiary gate and data pads may be formed at the same plane as the pixel electrodes such that the subsidiary gate and data pads are connected to the gate and data pads through the second and third contact holes.
Buffer conductive layers may be formed at the same plane as the data line assembly or the pixel electrodes while being positioned over the semiconductor pattern between the neighboring data lines.
In case the buffer conductive layer is placed at the same plane as the data line assembly, second contact holes are formed at the protective layer such that they expose the gate lines and the buffer conductive layers, and a connection pattern is formed at the same plane as the pixel electrodes. The connection pattern connects the gate lines to the buffer conductive layers through the second contact holes.
REFERENCES:
patent: 5128786 (1992-07-01), Yanagisawa
patent: 5510916 (1996-04-01), Takahashi
patent: 5926235 (1999-07-01), Han et al.
patent: 5956103 (1999-09-01), Ishiguro
patent: 6297862 (2001-10-01), Murade
patent: 7-159786 (1995-06-01), None
Choi Yong-Woo
Song Jang-Kun
Kim Robert H
McGuireWoods LLP
Samsung Electronics Co,. Ltd.
Schechter Andrew
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