Non-volatile-memory cell for electrically programmable read only

Details Non-volatile-memory cell for electrically programmable read only Non-volatile-memory cell for electrically programmable read only

1996-05-16

1998-01-13

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, 438266, H01L 21336

Patent

active

057078971

ABSTRACT:
A method for making an improved Electrically Programmable Read-Only-Memory (EPROM) device having non-volatile memory cells with enhanced capacitive coupling was achieved. The array of memory cells consists of a single field effect transistor (FET) having an additional floating gate. The FET is formed in a well etched into an insulating layer on the substrate surface. After forming the FET gate oxide, a polysilicon layer is patterned to form a trench-like floating gate with increased capacitive coupling. An interlevel dielectric layer is deposited. A second polysilicon layer is deposited in the well and chem/mech polished back to form the control gate. The insulating layer having the wells is selectively removed. Lightly doped source/drain areas, self-aligned to the FET gate electrodes, are implanted and after forming sidewall spacers on the gate electrodes, source/drain contacts and buried bit lines are formed by a second implant. An insulating layer is deposited over the array of FETs having contact openings to the FET control gates. Another polysilicon layer is deposited and patterned to form the word lines. The word lines and buried bit lines are connected to the peripheral circuits to complete the EPROM chip.

REFERENCES:
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patent: 5343063 (1994-08-01), Yuan et al.
patent: 5380672 (1995-01-01), Yuan et al.
patent: 5441908 (1995-08-01), Lee et al.
patent: 5631179 (1997-05-01), Sung et al.

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