Semiconductor memory device and associated data read method

Details Semiconductor memory device and associated data read method Semiconductor memory device and associated data read method

2003-05-30

2004-05-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000, C365S230080, C365S233100

Reexamination Certificate

active

06738295

ABSTRACT:

This application claims priority from Korean patent application No. 2002-45693 filed Aug. 1, 2002, and incorporated herein by reference.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of accurately reading data and an associated data read method.
2. Description of Related Art
In a double data rate (DDR) semiconductor memory device, an on time control and latch clock signals are generated responsive to an internal clock signal internally generated by a delay locked loop. The on time control signal controls a data output buffer. The latch clock signal determines data latching times are generate.
In a conventional DDR device, the data output buffer latches and outputs data only when the latch clock signal is generated after the on time control signal.
When the conventional DDR device operates at low frequency, the data output buffer properly outputs the data because the on time control signal is generated before the latch clock signal. In contrast, when the DDR device operates at high frequency, the data output buffer does not correctly output the data (e.g., data might be delayed) because the latch clock signal is generated before the on time control signal.
The on time control signal is generated before the latch clock signal during high frequency operation because the on time control signal is generated at a constant frequency without depending on the operating frequency of the semiconductor memory device. The latch clock signal, on the other hand, is generated responsive to the operating frequency of the semiconductor memory device. Accordingly, the latch clock signal might be inadvertently generated before the on time signal where the device operates in high frequency.
FIG. 1
is a block diagram of a data read path in a conventional DDR semiconductor memory device. The conventional DDR device includes a first and a second data banks
10
-
1
and
10
-
2
, sense amplifiers
12
-
1
and
12
-
2
, data output buffers
14
-
1
and
14
-
2
, a data output driver
16
, a delay locked loop
20
, a latch clock signal CLKDQF, CLFDQS generating circuit
24
, a clock signal (CLK
2
F CLK
2
S) generating circuit
22
, a latency signal (LAB) generating circuit
26
, an on time control signal (PTRSTF, PTRSTS) generating circuit
28
, and a mode setting circuit
30
.
The first memory bank
10
-
1
reads and writes data responsive to rising edge of a clock signal. The second memory bank
10
-
2
reads and writes data responsive to the falling edge of the clock signal (not shown).
The sense amplifier
12
-
1
amplifies the data read out from the first memory bank
10
-
1
and the sense amplifier
12
-
2
amplifies the data read out from the second memory bank
10
-
2
.
The data output buffer
14
-
1
receives an output signal of the sense amplifier
12
-
1
responsive to the on time control signal PTRSTF, and then buffers and outputs the received signal responsive to the latch clock signal CLKDQF. The data output buffer
14
-
2
receives an output signal of the sense amplifier
12
-
2
responsive to the on time control signal PTRSTF, and then buffers and outputs the received signal responsive to the latch clock signal CLKDQS.
The delay locked loop
20
receives the clock signal CLK and generates the clock signals CLK
1
F, CLK
1
S.
The clock signal generating circuit
2
receives the clock signals CLK
1
F and CLK
1
S and generates clock signals CLK
2
F and CLK
2
S. The latch clock signal generating circuit
24
generates the latch clock signals CLKDQF and CLKDQS responsive to the clock signals CLK
1
F, CLK
1
S and the column address strobe (CAS) latency signals CL
1
.
5
, CL
2
, CL
2
.
5
, CL
3
.
The latency signal generating circuit
26
generates a latency signal LAB responsive to the CAS latency signals CL
1
.
5
, CL
2
, CL
2
.
5
and CL
3
and the clock signals CLK
2
F and CLK
2
S.
The on time control signal generating circuit
28
receives the latency signal LAB responsive to the clock signals CLK
2
F, CLK
2
S and generates the on time control signals PTRSTF, PTRSTS.
The mode setting circuit
30
receives the CAS latency signals CL
1
.
5
, CL
2
, CL
2
.
5
and CL
3
input from address pins (not shown) during a mode setting operation.
FIG. 2
is a circuit diagram of a data output buffer embodiment. The conventional data output buffer comprises a data output buffer
14
-
1
including an input circuit
14
-
11
and a buffer/latch circuit
14
-
12
, and a data output buffer
14
-
2
including an input circuit
14
-
2
and a buffer/latch circuit
14
-
22
.
The input circuit
14
-
11
comprises an inverter I
1
, a NOR gate NOR
1
and a NAND gate NA
1
. The buffer/latch circuit
14
-
12
comprises an inverter I
3
, NAND gates NA
2
and NA
3
, NOR gates NOR
2
and NOR
3
, PMOS transistors P
1
and P
2
, NMOS transistors N
1
and N
2
and a latch L
1
comprising inverters I
5
and I
6
.
The input circuit
14
-
21
comprises an inverter I
2
, a NOR gate NOR
4
, and a NAND gate NA
4
. The buffer/latch circuit
14
-
22
comprises an inverter I
4
, NAND gates NA
5
and NA
6
, NOR gates NOR
5
and NOR
6
, PMOS transistors P
3
and P
4
, NMOS transistors N
3
and N
4
, and a latch L
2
comprising I
7
and I
8
.
The data output buffers
14
-
1
and
14
-
2
, each buffer one bit of data DOF or DOS. The data output buffer
14
-
1
operates as we describe below. The data output buffer
14
-
2
operates similarly to data output buffer
14
-
1
. T
When the on time control signal PTRSTF is at a logic “high” level is, the NOR gate NOR
1
and the NAND gate NA
1
invert the data DOF. That is, if the data DOF is at a logic “high” level, the NOR gate NOR
1
and the NAND gate NA
1
output the data DOF at a of logic “low” level. The NAND gates NA
2
and NA
3
generate logic “high” level signals. Accordingly, the PMOS transistors P
1
and P
2
are turned off. At this time, if the clock signal CLKDQF has the logic “high” level, the NOR gates NOR
2
and NOR
3
generate corresponding logic “high” level signals. Accordingly, the NMOS transistors N
1
and N
2
are turned on and thus logic “low” level signals are generated at a common node of the PMOS transistor P
1
and the NMOS transistor N
1
and a common node of the PMOS transistor P
2
and the NMOS transistor N
2
. The latches L
1
and L
2
invert and latch the logic “low” level signal, and then generate signals DOP and DON having logic “high” levels. On the other hand, if the clock signal CLKDQF has logic “low” level, the NAND gates NA
2
and NA
3
generate corresponding logic “high” level signals and the NOR gates NOR
2
and NOR
3
generate corresponding logic “low” level signals. Accordingly, the PMOS transistors P
1
and P
2
and the NMOS transistors N
1
and N
2
are turned off, and the latches L
1
and L
2
output the previously latched signals as the data DOP and DON.
On the other hand, when the on time control signal PTRSTF has a logic “low” level, the NOR gate NOR
1
generates a logic “low” level signal and the NAND gate NA
1
generates a logic “high” level signal. The NAND gate NA
2
generates a logic “high” level signal and the NOR gate NOR
3
generates a logic “low” level signal. Accordingly, the PMOS transistor P
1
and the NMOS transistor N
2
are turned off. If the clock signal CLKDQF has the logic “low” level, the NOR gate NOR
2
generates a logic “low” level signal and the NAND gate NA
3
generates a logic “high” level signal. Accordingly, the NMOS transistor N
1
and the PMOS transistor P
2
are turned off. The latches L
1
and L
2
output the latched data DOP and DON, respectively.
As described above, the data output buffer buffers and latches the data DOF and outputs the data DOP and DON.
When the on time control signal PTRSTF is at a logic “low” and the clock signal CLKDQF of the logic “high” level is applied, the NOR gate NOR
1
outputs the logic “low” level signal and the NAND gate NA
1
outputs the logic “high” level signal, so that the NAND gate NA
2
generates logic “high” level signal and the NOR gate NOR
3
gene

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