Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-23
2002-07-30
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000
Reexamination Certificate
active
06426253
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a system and method for fabricating integrated circuits (“IC”s), and more particularly to a system and method for forming a vertically oriented device in an integrated circuit.
BACKGROUND
The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices on a single semiconductor product.
Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less. There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device's horizontal dimensions. In addition, the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.
One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory (“DRAM”). A DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field-effect transistor (“FET”) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
Another way of providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.
To still further reduce the amount of planar area required for each cell, it has been proposed to use a vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell. In a typical design, the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench. A vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.
There are generally several problems, however, with prior art approaches to fabricating a vertical transistor in a DRAM cell. One difficult fabrication issue is that either the source or the drain of the vertical transistor must generally make electrical contact with the interior plate of the trench capacitor in order to form a basic memory cell circuit. This is typically accomplished through the formation of an asymmetrical buried strap junction on only one side of the trench capacitor. The buried strap electrically connects the interior plate of the capacitor to the source or drain of the vertical transistor. Creating an asymmetrical structure at some distance within the narrow trench has proved to be a difficult task in the prior art.
One prior art approach to fabricating the buried strap is to utilize a deep ultraviolet (“DUV”) mask process to aid in forming the asymmetrical buried strap. A DUV mask allows one portion of the trench to be processed differently from another portion of the trench, and thus enables the formation of an asymmetrical structure within the trench. DUV masks are expensive, however, and their use in the fabrication process should be kept to a minimum.
Another approach that has been suggested is the use of a high-aspect angled implantation process to aid in forming the buried strap. This approach also allows one portion of the trench to be processed differently than another portion of the trench, in this case because implanted and non-implanted variations of the same material may have very different processing characteristics. This difference may be used to one's advantage to form an asymmetrical structure within the trench. A processing difficulty with this approach, however, is that to reach a sufficient depth into the trench, the dopant must be implanted using carefully controlled high-angle implantation (e.g., 85 degrees or higher with respect to the substrate, but less than 90 degrees). In addition, the structure generally must have a high-aspect ratio (e.g., 10:1 or higher, height of mask sidewall to width of trench) to serve as a mask so that only a portion of the trench is doped by the implantation process (e.g., the upper portion of one side). This approach may be sensitive to process variations, and not sufficiently robust for a production environment.
Accordingly, there exists in the prior art a need for a less difficult and costly method of forming a vertical trench transistor connected to a trench capacitor via a buried strap junction, especially for use in a DRAM memory cell.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which an electrical connection to the interior of a deep trench is formed in an integrated circuit utilizing a low-angle dopant implantation to create a self-aligned mask over the trench. Preferably, the electrical connection, or buried strap, connects the interior plate of a trench capacitor to a terminal of a vertical trench transistor.
A low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. As used herein with respect to the implantation process, the term “low-angle” means about 80 degrees or less, preferably about 75 degrees or less, more preferably about 60 degrees or less, and most preferably between about 30 degrees and about 60 degrees. As used herein with respect to the implantation mask height to width ratio, the term “low-aspect” means about 4:1 or less, preferably about 3:1 or less, and more preferably about 2:1 or less. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material overlying or in the trench, leaving a self-aligned mask covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped a
Kudelka Stephan
Lee Brian S.
Michaelis Alexander
Schroeder Uwe
Tews Helmut Horst
Braden Stanton
Infineon Technologies A G
Nguyen Tuan H.
LandOfFree
Method of forming a vertically oriented device in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a vertically oriented device in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a vertically oriented device in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2843636