Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-04
2002-01-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S727000, C714S729000, C365S201000
Reexamination Certificate
active
06343365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a large-scale integrated circuit and a method of testing a board thereof, and more particularly to a large-scale integrated circuit, the structure of which has flip-flops that are serially connected, and a method of testing a board using a scan path.
2. Description of the Related Art
As is widely known, in recent years there has been a rapid increase in the scale of large-scale integrated circuits. A shift from bipolar large-scale integrated circuits designed with emphasis high speed to CMOS (complementary metal-oxide semiconductor) large-scale integrated circuits, which enable a high degree of integration and parallel processing forms the backdrop for this increase in the scale of large-scale integrated circuits.
Other factors include the achievement of high-density printed circuit boards that enable blind vias, and a shift away from quad flat packages, in which the electrical connections between a printed circuit board and a large-scale integrated circuit are made by means of a line of connections on each of four sides around a case of the large-scale integrated circuit, in favor of a PGA (pin grid array) or BGA (ball grid array), in which electrodes are arranged in a matrix immediately beneath the large-scale integrated circuit, thereby enabling the accommodation of a large number of pins.
With the appearance of high-density large-scale integrated circuits, it has become difficult to generate a test pattern suitable for board-level testing of a printed circuit board after large-scale integrated circuits have been mounted to the board, and the time required for test pattern generation has increased.
Along with these changes, the scan path length has increased and an amount of the test patterns has been increased, thereby causing an increase in the test time.
A full scan path
34
, as shown in
FIG. 3
, is an example of an easily testable circuit for the purpose of solving the above-noted problem.
The full scan path
34
is the series connection of all the flip-flops
32
and flip-flops
32
′ that originally existed within the large-scale integrated circuit
31
, regardless of whether or not they exist in the region of the input/output pins
33
, test data being scanned in and out via the scan in
35
and scan out
36
, thereby enabling to set an arbitrary internal condition thereof from outside the device, or to withdraw the internal condition therefrom and to perform observation thereof, at a certain point in time, it is easy to divide the internal circuit of the large-scale integrated circuit
1
and generate a test pattern therefor.
By employing a test that uses the full scan pattern
34
, it is not only possible, of course, to test the functions of the large-scale integrated circuit
31
, but also to perform tracing so as to identify what constituent component thereof has failed.
The full scan path
34
is simple, in that it can be generated in a single operation by the ATPG (automatic test pattern generator) of a CAD (computer aided design) system, without making a distinction with regard to individual flip-flops of the circuit.
However, with circuit scale being large, data generation times have become unrealistic and failure analysis procedures have become excessively deep, thereby imposing a limit on the failure detection rate that can be achieved in finite amount of time.
As shown in
FIG. 4
, there is a boundary scan path
47
that is used to achieve an easily testable circuit, this taking notice of only the connections between the large-scale integrated circuit
41
,
41
.
The boundary scan path
47
is the series connection of not only the circuitry parts (the part
49
that is outside the scope of the simulation, which includes the flip-flops
42
) that are originally part of the large-scale integrated circuit
41
, but also dedicated boundary scan
48
which is disposed in the region of the I/O pins
43
of the large-scale integrated circuit
41
, this being connected in series.
The boundary scan
48
is formed by such parts as a test data register that includes, for example, a scan register that is disposed in parallel with the input/output register, a TAP controller that receives a test command from a test access port and performs control of the execution of a series of procedures, a multiplexer that switches the routing of data between the scanning mode and the actual operating mode, and a decoder for test operating commands.
A board test that employs the boundary scan path
47
has become an IEEE Standard and, because test commands and the transitions between the states thereof have become standardized, from the standpoint of test development and test data generation, efficiency is achieved, without the need for each board test supplier to develop and understand a different language.
However, from the standpoint of the board producer, that is, the developer of the large-scale integrated circuit
41
, because it is necessary to devote 5% to 10% of valuable real estate within the large-scale integrated circuit to the purpose of testing, to achieve the desired circuit scale, it is necessary to have a large-scale integrated circuit
41
that is even larger, this increase in size causing an increase in delay times.
In the above-noted prior art, as a result of dramatic advances in the level of integration of LSI devices over those of the past, merely performing circuit division using a full scan path or a boundary scan path resulted in an increase in the size of the circuit, which is an object circuit for simulation procedure, and which led again to an increase in the time required to generate test pattern.
An addition problem is that, at the board level, the scan path length becomes long, thereby causing an increase in the test time.
If main object of a board-level test is the verification of connections between LSI devices, there is the problem that most parts of the generated test pattern do not contribute to the achievement of this object.
Accordingly, an object of the present invention is to provide a large-scale integrated circuit that has a scan path (hereinafter referred to as an I/O scan path) that is formed by a selective serial connection between only flip-flops each of which is in a region near the respective I/O pins of the LSI circuit (including those that are not directly connected to I/O pins but are rather connected thereto via several stages of logic), thereby enabling a shortening of the time required to generate a test pattern, and a shortening of the time required for the test time in board level test.
Another object of the present invention is to provide a board test method which facilitates the verification of connections between LSI circuits that are provided with an I/O scan path, in easy way.
In order to achieve the above-noted objects, a large-scale integrated circuit according to the present invention has a I/O scan path formed by the selective serial connection of only flip-flops that are in a region near I/O pins thereof.
Additionally, an LSI circuit according to the present invention is one having a structure that has a scan path of flip-flops connected in series, this scan path being divided between an I/O scan path
10
of the series connection of only flip-flops that are in a region near I/O pins and an internal scan path
11
of other flip-flops connected in series, and which also has a selector that selects either all the paths of the scan paths or only the paths of the I/O scan path.
Additionally, a large-scale integrated circuit according to the present invention is one having a structure that has a scan path of flip-flops connected in series, this scan path being divided between an I/O scan path
10
of only flip-flops that are in a region near I/O pins and an internal scan path
11
of other flip-flops connected in series, the above-noted LSI circuit also having a selector, one input of which is connected to another end of the above-noted I/O scan path and to one end of the above-noted internal scan path, the other input of which is
Ito Hiroo
Matsuzawa Hajime
De'cady Albert
Lamarre Guy
NEC Corporation
Sughrue & Mion, PLLC
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