Method of gate doping by ion implantation

Details Method of gate doping by ion implantation Method of gate doping by ion implantation

1998-08-31

2002-03-26

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S527000, C438S529000, C438S283000

Reexamination Certificate

active

06362055

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus of MOSFET gate doping by having separate drain/source dopant implant and gate dopant implant.
2. Background of the Invention
For conventional very-large scale integration (VLSI) complementary metal oxide semiconductor (CMOS) technology, the gate electrode is doped at the same time when the source and the drain are doped. For such conventional CMOS devices, the gate material is formed from either polysilicon (poly-Si), polysilicon germanium (poly-SiGe), or amorphous silicon (&agr;-Si).
One of the disadvantages of the conventional approach is that the gate implantation dopant species has to be the same as that of the source and the drain, since the doping for the gate, source and drain is performed at the same time.
Another of the disadvantages of the conventional approach is caused due to the projections of the gate implantation and the source/drain implantation being close to each other. Because the source/drain junction depth is typically smaller than the gate stack thickness, the gate implantation may not be deep enough to suppress the gate depletion near the gate electrode/gate oxide interface. This gate depletion effect causes a degradation in the drive current of the transistor that is formed by the conventional approach.
Still another of the disadvantages of the conventional approach is that the gate implant has the same rapid thermal annealing (RTA) process as that of the source and drain. Because the source/drain (S/D) RTA process is limited by the shallow junction requirement, insufficient annealing may occur to the gate dopant, thereby causing high gate sheet resistance and gate depletion effect.
SUMMARY OF THE INVENTION
An object of the present invention is to form a MOSFET in which the gate depletion effect is lessened or eliminated.
Another object of the present invention is to form a MOSFET in which the gate dopant implant species is different from the source/drain dopant implant species.
Yet another object of the present invention is to form a MOSFET in which sufficient annealing is provided to the gate dopant.
These and other objects and advantages of the present invention are achieved by a method of forming a semiconductor device on a semiconductor substrate, the semiconductor device including a first MOSFET of a first conductivity type and a second MOSFET of a second conductivity type. The method includes a step of forming a gate oxide layer on the semiconductor substrate. The method also includes a step of forming a gate material on the gate oxide layer, where the gate material is one of poly-Si, poly-SiGe, and &agr;-Si. The method further includes a step of providing a first photo-resist on the gate material, the first photo-resist having at least one window over a first portion of the gate material. The method still further includes a step of providing a photo-lithography with an n+ type dopant, to thereby expose and implant the first portion of the gate material with the n+ type dopant.
The method also includes a step of striping the first photo-resist. The method further includes a step of providing a second photo-resist on the gate material, the second photo-resist having at least one window over a second portion of the gate material, the second portion being separate from the first portion. The method still further includes a step of providing a photo-lithography with a p+ type dopant, to thereby expose and implant the second portion of the gate material with the p+ type dopant. The method also includes a step of striping the second photo-resist, thereby exposing all portions of the gate material.
The method still further includes a step of depositing tungsten silicide (WSi
x
) onto the gate material. The method also includes a step of providing a third photo-resist above the first and second portions of the gate material. The method further includes a step of etching the semiconductor device down to the semiconductor substrate, thereby leaving a first gate stack corresponding to a location of the first portion of the gate material, and a second gate stack corresponding to a location of the second portion of the gate material. The method still further includes a step of striping the third photo-resist, wherein the first gate stack corresponds to a gate of the first MOSFET of the first conductivity type, and the second MOSFET corresponds to a gate of the second MOSFET of the second conductivity type.
The above-mentioned objects and other advantages may also be achieved by a semiconductor device, which includes a first MOSFET of a first conductivity type and a second MOSFET of a second conductivity type. The first MOSFET includes a first gate stack having a first region of the first conductivity type having a gate material of a first concentration disposed therein. The second MOSFET includes a second gate stack having a second region of the second conductivity type having the gate material of a second concentration different from the first concentration. The gate material is one of poly-Si, poly-SiGe, and &agr;-Si.


REFERENCES:
patent: 5683941 (1997-11-01), Kao et al.
patent: 5723356 (1998-03-01), Tsukamoto
patent: 6051459 (2000-04-01), Gardner et al.
patent: 6054354 (2000-04-01), Nowak et al.

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