Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-31
2011-05-31
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
07954029
ABSTRACT:
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing a memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.
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Micro)n Technology, Inc.
Ton David
TraskBritt
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