Methods for forming capacitor structures including etching pits

Details Methods for forming capacitor structures including etching pits Methods for forming capacitor structures including etching pits

1996-10-09

2001-02-27

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S398000

Reexamination Certificate

active

06194263

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit devices and more particularly to methods for forming capacitor structures for integrated circuit devices.
BACKGROUND OF THE INVENTION
As dynamic random access memories (DRAMs) become more highly integrated, the area available for each memory cell generally decreases thus resulting in smaller memory cell capacitors. Decreases in the memory cell capacitance may thus reduce the stability of a memory device. In particular, a decrease in the memory cell capacitance may lower the read and write tolerances for the memory cell, increase a soft error rate, and make low voltage operations more difficult. Accordingly, there continues to exist a need in the art to provide memory cell capacitors which maintain a sufficient capacitance despite reductions in surface area available for the capacitor.
In general, a 64 Mb DRAM may have a memory cell area of approximately 1.5 &mgr;m
2
. Accordingly, it may be difficult to provide a sufficient memory cell capacitance even when using a two-dimensional stacked capacitor structure with a dielectric material such as Ta
2
O
5
. Three-dimensional capacitor structures have thus been suggested to increase the memory cell capacitance. For example, a capacitor electrode having a fin structure has been suggested by Fujitsu, a capacitor electrode having a box structure has been suggested by Toshiba, and a capacitor electrode having a cylindrical structure has been suggested by Mitsubishi.
The fabrication of a capacitor with a three-dimensional structure, however, may be difficult, and defects may occur. Research has also been directed toward the development of dielectric materials with high dielectric constants which can be used to increase the capacitance of a memory cell capacitor. These materials with high dielectric constants, however, may also be difficult to fabricate in a memory device.
Research has also been directed toward methods for fabricating ridge and valley type lower electrodes wherein a surface area of an electrode is increased thus increasing the capacitance. For example, multiple bumps of hemispherical grained-silicon (HSG-Si) can be formed on the surface of a capacitor electrode to form ridges and valleys on the surface of the electrode thereby increasing the surface area of the electrode. Several methods are known for forming hemispherical grained-silicon bumps on electrodes. First, a chemical vapor deposition step can be used to deposit silicon at a temperature where a phase transformation from amorphous silicon to polysilicon occurs. Second, amorphous silicon can be annealed without a native oxide layer in a vacuum. Third, a seeding step can be used to form hemispherical grained-silicon (HSG-Si) bumps using a low pressure chemical vapor deposition (LPCVD) with SiH
4
gas or Si
2
H
6
gas, or by irradiating a beam of SiH
4
or Si
2
H
6
on amorphous silicon. These seeds can then be grown to form enlarged HSG-Si bumps.
In particular, it has been reported that the surface area of a capacitor electrode can be increased using the seeding method to form a ridge and valley type structure. See, H. Watanabe et al.,
A New Cylindrical Capacitor Using Hemispherical Grained Si
(
HSG
-
Si
)
For
256
Mb DRAMs
, IEDM, 1992, pp. 259-262.
FIGS. 1 through 3
are cross-sectional views illustrating steps of a method for fabricating a capacitor for a DRAM according to the prior art. As will be understood by one having skill in the art, a dynamic random access memory includes a plurality of memory cells, and each memory cell includes a storage electrode and a memory cell access transistor which connects the memory cell capacitor to a bit line in response to an activation signal on a word line. As shown, the memory cell access transistor includes a source/drain region
12
and a gate made up of gate electrode
16
and a gate insulating layer
14
. A second source/drain of the memory cell access transistor is connected to a bit line, and a word line is connected to the gate electrode
16
.
As shown in
FIG. 1
, an insulating layer
20
such as a silicon oxide layer is formed on the semiconductor substrate
10
and the memory cell access transistor. The insulating layer is then patterned using a photolithographic technique to form a contact hole exposing a portion of the semiconductor substrate
10
. In particular, the contact hole exposes the source/drain
12
of the memory cell access transistor.
A doped amorphous silicon layer is then formed on the insulating layer
20
, and this insulating layer
20
fills the contact hole to make electrical contact with the substrate
10
. This silicon layer can then be patterned to provide the capacitor electrode
40
having a cylindrical structure. This capacitor electrode
40
is thus connected to the source/drain
12
of the memory cell access transistor through the contact hole.
Hemispherical grained-silicon seeds
50
a
and
50
b
are respectively grown on the capacitor electrode
40
and the insulating layer
20
as shown in FIG.
2
. In particular, the HSG-Si seeds can be formed on the capacitor electrode
40
using a low pressure chemical vapor deposition (LPCVD) technique with a silicon source gas. Because the HSG-Si seeds are formed first at a portion of the capacitor electrode
40
with a relatively high surface energy, the HSG-Si seeds will be scattered on the surface of the capacitor electrode
40
. In addition, the silicon source gas can include SiH
4
, Si
2
H
6
, Si
3
H
8
, SiH
2
Cl
2
, or SiH
2
Cl
2
. Alternately, the HSG-Si seeds may be formed on the capacitor electrode
40
by irradiating a beam of the silicon source gas on the surface of the substrate including the capacitor electrode
40
.
Because the selectivity of HSG-Si seed formation is relatively low, the HSG-Si seeds may be formed on the insulating layer
20
in addition to the capacitor electrode
40
. Accordingly, HSG-Si seeds on the capacitor electrode
40
will be identified by the reference number
50
a
, and HSG-Si seeds formed on the insulating layer
20
will be identified with the reference number
50
b.
The structure is then heated to selectively grow the HSG-Si seeds
50
a
on the capacitor electrode
40
thus forming the enlarged HSG-Si bumps
50
c
on the capacitor electrode
40
as shown in FIG.
3
. Accordingly, the surface area of the capacitor electrode
40
can be increased. Because the HSG-Si seeds
50
a
on the capacitor electrode
40
grow by receiving silicon from the capacitor electrode
40
and because the HSG-Si seeds
50
b
on the insulating layer
20
do not receive the silicon required for growth, only the HSG-Si seeds
50
a
on the capacitor electrode
40
grow to form the enlarged HSG-Si bumps
50
c.
As further shown in
FIG. 3
, the HSG-Si seeds
50
b
remain on the insulating layer
20
. Accordingly, adjacent capacitor electrodes may be electrically shorted by the HSG-Si seeds
50
b
on the insulating layer
20
resulting in misoperations of the memory device. In addition, it may be difficult to obtain a desired cell capacitance because the increase in surface area of the capacitor electrode is dependent on the growth of the HSG-Si seeds
50
a.
A dielectric layer and a second capacitor electrode are then formed on the first capacitor electrode
40
. The dielectric layer and the second electrode may extend across the surface covering multiple first capacitor electrodes
40
.
As discussed above, the HSG-Si seeds
50
b
on the insulating layer
20
may remain so that adjacent capacitor electrodes
40
may be susceptible to electric shorts. In addition, further increases in memory cell capacitance may be desired to provide still greater memory cell capacitance. Accordingly, there continues to exist a need in the art for improved methods for forming capacitor structures for memory devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods for forming capacitor structures.
It is another object of the present invention to provide methods for forming a capacitor having increa

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