Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-01-13
2001-09-18
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S108000, C438S125000, C438S126000, C257S678000, C257S686000, C257S696000, C257S723000, C257S758000, C257S777000
Reexamination Certificate
active
06291260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a crack-preventive substrate and process for fabricating a solder mask, and more particularly to a crack-preventive substrate and process that can prevent the solder mask in the device site region from cracking.
2. Description of Related Art
The packaging process of semiconductor is the final step in manufacturing IC (integrated circuit) products. The objectives of the packaging process of semiconductor are to provide a medium of electrical connection between the die and PCB (printed circuit board) or between the die and other appropriate devices, as well as to protect the die from being damaged or contaminated. As far as the general BGA (Ball Grid Array) packaging process is concerned, the devices are assembled by first mounting the dies on a surface at individual device site on a substrate strip, then, performing electrical connection between the dies and the substrate. Afterwards, the devices are assembled by performing encapsulating process to encase the devices etc. by molding compound, subsequently, performing a solder-ball planting process on the another surface of the substrate strip to form solder balls of BGA package. Finally, a singulating process is performed to separate the encapsulated devices from the substrate strip, thus to complete the assembling process of a BGA package.
In the conventional package, a solder mask layer is formed on each surface of the substrate strip for the purpose of protecting the circuitry on the substrate from being damaged or contaminated during the solder-ball planting process and plating process. In additions, the forming of the solder mask layer is to effectively isolate each of the circuit region lest the unnecessary electrical connections be occurred in order that the substrate has relatively high reliability and yield to facilitate the subsequent packaging process.
In general, the footprint of a die-bonded device site is in rectangular shape, and the device site is connected to the substrate at the four-corner only. Moreover, a typical punching tool for a singulating process has a right-angle cutting edge corresponding to each corner of the device site. In the singulating process, the device will be excised from the substrate through the four-corner of the device site.
During a series of packaging process, the stresses resulted from each handling step and the thermal stresses will generate crack lines on the solder mask layer at the perimeter of the substrate. The crack lines started from the perimeter of the substrate will develop through the connection between the substrate and the device site toward the device site, thereby, will cause the exposure of the circuit region of the device site. Consequently, through the gap of the crack lines, the device will be damaged and contaminated by the exterior moisture, dust etc. that will cause the cracking of the solder mask layer in the subsequent high temperature process, thus the yield will be lowered.
SUMMARY OF THE INVENTION
Therefore, the present invention is to provide a crack-preventive substrate for fabricating a solder mask in a device site region that includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is also divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”.
The present also provides a crack-preventive process for fabricating a solder mask in a device site region wherein the process comprises firstly providing a substrate that has a top surface and a bottom surface, and the substrate also includes a device site region and a periphery region. Then, the process provides forming a solder mask layer on the top surface and bottom surface of the substrate. The solder mask layer forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. The bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. Subsequently, the process provides mounting a die in the device site region on the top surface of the substrate. Then, it provides performing an encapsulating process in the device site region on the top surface of the substrate and performing a solder-ball planting process. Finally, the process provides performing a singulating process to separate the device site region and the periphery region.
Normally, crack lines will be generated in the solder mask layer at the perimeter of the substrate by the subsequent processes of die attachment, wire bonding, encapsulating, and solder-ball planting etc. The crack line can also be generated due to the unequal thermal stresses resulted from the difference in the coefficient of thermal expansion of the bonding of the two different kinds material. According to a preferred embodiment of the present invention, the above-mentioned bare area encloses the device site region such that the solder mask in the device site region and the solder mask in the periphery region are separated, thereby, the crack lines. can not develop to the device site region nor can they develop into the encapsulated packages. Therefore, the problems of being relatively low in yield and relatively low in reliability resulted from the crack line generation in the solder mask layer can thus be resolved.
REFERENCES:
patent: 4652513 (1987-03-01), Pentak et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 5953589 (1999-09-01), Shim et al.
patent: 6097091 (2000-08-01), Ohsumi
Chen April
Her Tzong-Dar
Huang Chien-Ping
Elms Richard
Huang Jiawei
J.C. Patents
Luu Pho
Siliconware Precision Industries Co., LTD.
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