Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-18
2001-06-12
Bowers, Charles (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S160000, C438S571000, C438S486000
Reexamination Certificate
active
06245602
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a self-aligned polysilicon thin film transistor and its method of fabrication, and more particularly a top gate self-aligned polysilicon thin film transistor using a dummy gate and its method of fabrication.
BACKGROUND OF THE INVENTION
In current active matrix liquid crystal display (LCD) technology, each pixel is addressed by a transistor fabricated on a transparent glass substrate. This thin film transistor (TFT) serves as a switch controlling the charging and discharging of a liquid crystal cell to determine the amount of light transmitted. Conventional TFTs are either amorphous silicon (a-Si) or polysilicon (poly-Si). Currently, a-Si TFTs are the dominant technology used for active matrix liquid crystal displays. Poly-Si TFTs, however, offer several advantages over a-Si technology. First, poly-Si TFTs displays are less costly, since its driver circuits can be formed at the same time on the same substrate as the panel. Second, poly-Si can provide higher aperture ratio displays at high pixel densities. Third, the carrier mobility of poly-Si TFTs are, at the present time, more than 200 times that of a-Si TFTs. And since poly-Si TFTs operate at higher speeds and frequencies, additional circuits can be fabricated on the periphery of the display reducing production yield problems and lowering the cost of the display. Another advantage of poly-Si technology is reduced TFT size which allows the light blocking areas of the display to be minimized resulting in higher brightness and resolution.
A conventional top gate self-aligned poly-Si TFT is shown in
FIG. 1. A
layer of active silicon is deposited onto a fused quartz substrate (
101
) by, for example, low-pressure chemical vapor deposition (LPCVD). This layer is then annealed at a temperature of 600° C. for four hours in a nitrogen atmosphere to cause the amorphous silicon to crystallize into polysilicon (
102
).
The polycrystalline silicon layer is then patterned into an island. A gate oxide layer (
103
) is then deposited over the polysilicon layer and a polysilicon layer or metal layer of, for example chromium, is deposited over the gate oxide layer, pattemed, and etched to form a gate (
104
). Ion implantation is used to cause dopants such as phosphorous ions to penetrate the oxide layer (
103
) and settle into the polysilicon (
102
), except where the dopants are blocked by the gate (
104
). This forms N+type source and drain regions in the polycrystalline silicon layer. A dielectric layer (
105
) of low temperature silicon oxide (LTO) is then deposited by LPCVD. The structure is then annealed again to activate the source and drain regions. In the resultant structure, source and drain regions (
107
) and (
108
) become heavily doped polysilicon while channel region (
109
) remains undoped and exactly aligned with the gate.
To complete the top gate poly-Si TFT via holes are etched through the LTO layer (
105
) and the gate oxide layer (
103
) down to the source/drain regions, filled with conductive plugs (
106
), and connected to other parts of the circuit (not shown). Finally, a hydrogen passivation is carried out for about 8 hours in a parallel-plate plasma reactor at a substrate temperature of 350° C. in an H
2
and Ar gas mixture at a power density of 0.21 W/Cm
2
and a frequency of 30 kHz. This allows hydrogen atoms to diffuse through the LTO (
105
) layer to reach the channel region of the polysilicon.
This prior art method, however, suffers several limitations. Ion implantation damages the silicon layer and it must be regrown using a higher anneal temperature that may not be compatible with low temperature glass substrates that are desirable because of lower cost. Furthermore, the long hydrogenation step adds cost and time to the process.
U.S. Pat. No. 5,602,047 (the '047 patent) discloses a method for making a bottom gate TFT using an excimer laser that simultaneously crystallizes the active silicon and activates the source-drain region. The TFT disclosed in the ′047 patent, however, is a “bottom gate” structure. In contrast to the “top gate” structure previously described in which the gate electrode and oxide layer reside over the channel region, a “bottom gate” TFT has a gate electrode and oxide layer under the channel region. Bottom gate structures typically use a metal gate of aluminum, tantalum, chromium or molybdenum. Top gate structures are generally preferred over bottom gate structures which suffer performance problems because the highest quality (the top) portion of the active layer is not against the gate dielectric. Additionally, the use of a metal gate can cause problems due to the differences in the coefficient of thermal expansion such as cracking at the interface where laser light is reflected by the metal gate and absorbed by the substrate.
In light of the foregoing, there is a need for a method to make self-aligned top gate poly-Si TFTs that allows the use of low temperature substrates and requires only a single laser anneal to activate the source-drain region and to crystallize the active silicon.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of making a self-aligned polysilicon thin film transistor. The method includes the steps of providing a substrate that is optically transparent with a top surface, depositing a dummy gate on the top surface of the substrate, and depositing an isolation oxide layer. Next, an active silicon layer is deposited over the isolation oxide, a mask layer is deposited over the active silicon layer, and the mask layer is exposed to radiation directed to pass first through the bottom surface where the dummy gate acts as an optical mask. The mask layer is then developed to form a mask in exact alignment with the dummy gate. Dopant material is implanted to form a source-drain region, the mask is removed, and laser annealing to crystallize the active layer into polysilicon and to activate the source-drain regions. A gate oxide layer is then deposited over the polysilicon layer and an n+gate is deposited over the gate oxide layer. A photoresist layer is deposited and exposed to radiation directed to pass first through the bottom surface where the dummy gate acts as an optical mask. The photoresist layer is developed to form a photoresist mask to define the gate, a first passivation layer is deposited, and contact openings made. Finally, a metal layer is deposited on the polysilicon to contact the source-drain region, pattemed, and etched so it does not overlap the gate oxide. The metal layer and polysilicon are coated with a second passivation layer. Bond pads are then etched and formed through the passivation layer to the metal layer.
In another aspect, the invention is directed to a self-aligned polysilicon thin film transistor comprising an optically transparent substrate, a dummy gate, an isolation oxide layer, a doped polysilicon layer having a doped source, a doped drain, and an undoped channel, a gate oxide layer; and a self-aligned conductive gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description serve to explain the principles of the invention.
REFERENCES:
patent: 4692994 (1987-09-01), Moniwa et al.
patent: 4811076 (1989-03-01), Tigelaar
patent: 4811078 (1989-03-01), Tigelaar et al.
patent: 4894693 (1990-01-01), Tigelaar et al.
patent: 5733804 (1998-03-01), Hack et al.
patent: 5894137 (1999-04-01), Yamazaki et al.
Fulks Ronald T.
Ho Jackson
Bowers Charles
Finnegan Henderson Farabow Garrett & Dunner LLP
Schillinger Laura M
Xerox Corporation
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