Coating apparatus – Gas or vapor deposition – With treating means
Utility Patent
1992-08-13
2001-01-02
Bueker, Richard (Department: 1763)
Coating apparatus
Gas or vapor deposition
With treating means
C118S715000, C118S724000, C118S725000, C118S729000, C156S345420
Utility Patent
active
06167834
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a reactor and methods for performing single and in-situ multiple integrated circuit processing steps, including thermal CVD, plasma-enhanced chemical vapor deposition (PECVD), reactor self-cleaning, film etchback, and modification of profile or other film property by sputtering. The present invention also relates to a process for forming conformal, planar dielectric layers on integrated circuit wafers and to an in-situ multi-step process for forming conformal, planar dielectric layers that are suitable for use as interlevel dielectrics for multi-layer metallization interconnects.
I. Reactor
The early gas chemistry deposition reactors that were applied to semiconductor integrated circuit fabrication used relatively high temperature, thermally-activated chemistry to deposit from a gas onto a heated substrate. Such chemical vapor deposition of a solid onto a surface involves a heterogeneous surface reaction of gaseous species that adsorb onto the surface. The rate of film growth and the film quality depend on the wafer surface temperature and on the gaseous species available.
More recently, low temperature plasma-enhanced deposition and etching techniques have been developed for forming diverse materials, including metals such as aluminum and tungsten, dielectric films such as silicon nitride and silicon dioxide, and semiconductor films such as silicon.
The plasma used in the available plasma-enhanced chemical vapor deposition processes is a low pressure reactant gas discharge which is developed in an RF field. The plasma is, by definition, an electrically neutral ionized gas in which there are equal number densities of electrons and ions. At the relatively low pressures used in PECVD, the discharge is in the “glow” region and the electron energies can be quite high relative to heavy particle energies. The very high electron temperatures increase the density of disassociated species within the plasma which are available for deposition on nearby surfaces (such as substrates). The enhanced supply of reactive free radicals in the PECVD processes makes possible the deposition of dense, good quality films at lower temperatures and at faster deposition rates (300-400 Angstroms per minute) than are typically possible using purely thermally-activated CVD processes (100-200 Angstroms per minute). However, the deposition rates available using conventional plasma-enhanced processes are still relatively low.
Presently, batch-type reactors are used in most commercial PECVD applications. The batch reactors process a relatively large number of wafers at once and, thus, provide relatively high throughput despite the low deposition rates. However, single-wafer reactors have certain advantages, such as the lack of within-batch uniformity problems, which make such reactors attractive, particularly for large, expensive wafers such as 5-8 inch diameter wafers. In addition, and quite obviously, increasing the deposition rate and throughput of such single wafer reactors would further increase their range of useful applications.
II. Thermal CVD of SiO
2
; Planarization Process
Recently, integrated circuit (IC) technology has advanced from large scale integration (LSI) to very large scale integration (VLSI) and is projected to grow to ultra-large integration (ULSI) over the next several years. This advancement in monolithic circuit integration has been made possible by improvements in the manufacturing equipment as well as in the materials and methods used in processing semiconductor wafers into IC chips. However, the incorporation into IC chips of, first, increasingly complex devices and circuits and, second, greater device densities and smaller minimum feature sizes and smaller separations, imposes increasingly stringent requirements on the basic integrated circuit fabrication steps of masking, film formation, doping and etching.
As an example of the increasing complexity, it is projected that, shortly, typical MOS (metal oxide semiconductor) memory circuits will contain two levels of metal interconnect layers, while MOS logic circuits may well use two to three metal interconnect layers and bipolar digital circuits may require three to four such layers. The increasing complexity, thickness/depth and small size of such multiple interconnect levels make it increasingly difficult to fabricate the required conformal, planar interlevel dielectric layers materials such as silicon dioxide that support and electrically isolate such metal interconnect layers.
The difficulty in forming planarized conformal coatings on small stepped surface topographies is illustrated in FIG.
16
. There, a first film such as a conductor layer
171
has been formed over the existing stepped topography of a partially completed integrated circuit (not shown) and is undergoing the deposition of an interlayer dielectric layer
172
such as silicon dioxide. This is done preparatory to the formation of a second level conductor layer (not shown). Typically, where the mean-free path of the depositing active species is long compared to the step dimensions and where there is no rapid surface migration, the deposition rates at the bottom
173
, the sides
174
and the top
175
of the stepped topography are proportional to the associated arrival angles. The bottom and side arrival angles are a function of and are limited by the depth and small width of the trench. Thus, for very narrow and/or deep geometries the thickness of the bottom layer
173
tends to be deposited to a lesser thickness than is the side layer
174
which, in turn, is less than the thickness of top layer
175
.
Increasing the pressure used in the deposition process typically will increase the collision rate of the active species and decrease the mean-free path. This would increase the arrival angles and, thus, increase the deposition rate at the sidewalls
714
and bottom
173
of the trench or step. However, and referring to
FIG. 17A
, this also increases the arrival angle and associated deposition rate at stepped corners
176
.
For steps separated by a wide trench, the resulting inwardly sloping film configuration forms cusps
177
—
177
at the sidewall-bottom interface. It is difficult to form conformal metal and/or dielectric layers over such topographies. As a consequence, it is necessary to separately planarize the topography.
In addition, and referring to
FIG. 17B
, where the steps are separated by a narrow trench, for example, in dense 256 kilobit VLSI structures, the increased deposition rate at the corner
176
encloses a void
178
. Such voids are exposed by subsequent planarization procedures and may allow the second level conductor to penetrate and run along the void and short the conductors and devices along the void.
SUMMARY OF THE INVENTION
Objects
In view of the above discussion, it is one object to provide a semiconductor processing reactor which provides uniform deposition over a wide range of pressures, including very high pressures.
It is another related object to provide a versatile single wafer semiconductor processing reactor which can be used for a multiplicity of processes including thermal chemical vapor deposition, plasma-enhanced chemical vapor deposition, plasma-assisted etchback, plasma self-cleaning and sputter topography modification, either alone or in-situ in a multiple process sequence.
It is a related object to provide such a reactor which accomplishes the above objectives and also is adapted for using unstable gases such as TEOS and ozone.
It is another object of the present invention to provide a process for forming highly conformal silicon dioxide layers, even over small dimension stepped topographies in VLSI and ULSI devices, using ozone and TEOS gas chemistry and thermal CVD.
It is also an object of the present invention to provide a planarization process which provides excellent conformal coverage and eliminates cusps and voids.
It is still another object of the present invention to provide a planarization process which can be performed in-situ using a multiple numb
Adamik John A.
Collins Kenneth S.
Law Kam S.
Leung Cissy
Maydan Dan
Applied Materials Inc.
Bueker Richard
Morris Birgit
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