Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-14
2001-08-07
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06272656
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices including sequence circuits such as flip-flops and/or latches as well as testing method for use therewith. More particularly, the invention relates to a semiconductor integrated circuit capable of changing or varying the state of a circuit block of less controllability along with a test method therefor.
2. Description of the Prior Art
Conventionally, the so-called “scan-pass” test method has been well known as one of test facilitation schemes for semiconductor integrated circuits.
This scan-pass test method is for achieving facilitation of test procedures of semiconductor integrated circuits by replacing part or the whole of flip-flops which are sequence circuits in a semiconductor integrated circuit with a scannable flip-flop to provide a shift-register configuration while treating the remaining portions other than such one or more shift registers as a combination circuit thereby controlling the shift registers.
More than one latch may be also present in the sequence circuit other than the flip-flops. In cases where this semiconductor integrated circuit including a plurality of latches is tested by the scan-pass test method, two typical approaches have been known as will be described below.
The first approach is to perform the intended scan-pass test procedures by rendering the latch's enable signal active to let the latches operate with their operation mode being fixed in a “through” mode. This approach is to make latches combination circuits. The second approach is such that it is based on implementation of latches with a flop-flop configuration, wherein another latch is provided at the succeeding or post stage of a latch while regarding the pre-stage one as a “master” latch and also regarding its post stage as a “slave” latch operable as a flip-flop, whereby such flip-flop is accommodated into a shift register to thereby perform the scan-pass test.
In addition, with the scan-pass test method, when setting data into the shift register configuration, since this data setting is carried out through a shifting operation synchronized with a single clock, it is required that remedy against clock skew be employed in a way such that a buffer which reserves gain for a hold time period is inserted between neighboring flip-flops; or alternatively, for a non-synchronous circuit block in the circuitry, the circuit configuration is modified causing it to perform a synchronized operation with such clock during test operations.
However, in the prior known scan-pass test method, detection of defects near or around latches can become deficient due to the fact that the latches must be operatively fixed in the “through” mode according to the scheme of making latch to combination circuit. Furthermore, a feedback loop containing therein a latch or latches will possibly be formed in some cases, which would result in deficiency of defect detectivity also; accordingly, it has been difficult to obtain high defect detectability. On the other hand, with the latch-to-flip/flop function-change or “transmutation” scheme, an extra latch must be added per latch so that it suffers from a problem in that the area overhead can increase in circuitry which employs therein multiple latches.
In addition, concerning the scan-pass test method, the technique for inserting the buffer in order to attain the remedy against clock-skew stated supra is associated with a problem: when inserting buffers among all the flip-flops, the resulting area overhead increases; on the other hand, if such buffers are selectively inserted then the static analysis of circuitry should be required.
Another problem encountered with the prior art approaches is that with the aforementioned scheme for letting the non-synchronous circuit block operate as a synchronization circuit in the scan-pass test method, if a great number of non-synchronous circuit blocks are contained then the circuitry's area overhead can increase, which results in an extra delay taking place in a clock system thereby causing generation of extra process steps during design procedures in order to successfully meet the circuit specifications required.
Additionally in the recent years, semiconductor integrated circuits employing CMOS technology are the major devices in the art to which the invention pertains. In such semiconductor integrated circuits, small power supply current flows when circuitry is of no abnormality; it can thus be seen that the circuitry must contain certain abnormalities in cases power supply current greater in magnitude than or equal to a predefined level rushes to flow therein. In view of this fact, as one of the procedures for determining whether a semiconductor integrated circuit under inspection is acceptable or rejectable in quality, a test method may be effective which includes the steps of applying a test pattern for use in evaluation of the to-be-tested circuit of such semiconductor integrated circuit while at the same time monitoring the power supply current of the semiconductor integrated circuit. However, in order to increase the defect detectability of semiconductor integrated circuits, creation of a specific test pattern is required for use in sufficiently controlling the state or condition (whether in the ON state or in the OFF state) of elements which constitute the circuit being tested. In recent years, there is a problem which follows: as semiconductor integrated circuits increase both in functionality and in integration density, preparation of such test pattern becomes more difficult.
SUMMARY OF THE INVENTION
The present invention has been made by taking into consideration the technical background stated above, and its primary object is to provide a semiconductor integrated circuit capable of achieving high defect detectability and also facilitating the productivity of test patterns while reducing or minimizing the circuit area and also provide a testing method for use therewith.
To attain the foregoing object the instant invention provides a semiconductor integrated circuit which is featured by including a plurality of pairs of sequence circuit and selector circuit and further including a control circuit, wherein each of the sequence circuits is operable to store therein an operation result of internal circuitry of the semiconductor integrated circuit whereas each selector circuit is responsive to a control signal for selecting one of the data being stored in its associated sequence circuit and an inverted version of the data, and wherein the control circuit is responsible for controlling the selector circuits that constitute the plurality of pairs by counting up clocks or successively dividing the clocks to thereby provide a clock count value for use in controlling the selector circuits.
In prior known semiconductor integrated circuits, although the scan-pass testing method has been employed as one of the test facilitation schemes, the prior art is faced with the risk of an increase in area of circuitry for use in execution of the test procedures and an inability to obtain high defect detectability. On the contrary, with the semiconductor integrated circuit in accordance with the present invention, it becomes possible to permit flexible inputting of a test pattern comprised of the data and inverted data to a circuit being tested. This can be said because the semiconductor integrated circuit is specifically designed for the test to make use of a sequence circuit equipped therein for use during a standard operation thereby enabling selective outputting to the to-be-tested circuit one of the data being stored in the sequence circuit and an inverted version of such data. With such an arrangement, it is possible to well control the state of elements constituting such to-be-tested circuit while simultaneously suppressing or minimizing an increase in area of circuitry for testing. This in turn makes it possible to increase the defect detectability of the semiconductor integrated circuit to th
De'cady Albert
Kawasaki Steel Corporation
Oliff & Berridg,e PLC
Ton David
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