Method for increasing DRAM capacitance via use of a roughened su

Details Method for increasing DRAM capacitance via use of a roughened su Method for increasing DRAM capacitance via use of a roughened su

1998-02-23

1999-01-12

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, 438502, 438581, 438630, H01L 248242

Patent

active

058588388

ABSTRACT:
A method for increasing the surface area of a polysilicon storage node electrode, used as a component for a DRAM stacked capacitor structure, has been developed. The method features forming a metal silicide layer, on the top surface of the polysilicon storage node electrode, locally consuming regions of underlying polysilicon during the metal silicide formation. Removal of the metal silicide layer, from the surface of the polysilicon storage node electrode, results in a roughened surface, comprised of crevices in the top surface of the polysilicon storage node electrode, in regions in which localized metal silicide formation had occurred. The crevices in the top surface of the polysilicon storage node electrode result in surface area increases, when compared to counterparts fabricated using smooth polysilicon surfaces.

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