Yuen Hung Chan

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Array data input latch and data clocking scheme

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Method and apparatus for controlling the timing of precharge...

Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate

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Multifunctional latch circuit for use with both SRAM array...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Precharged bit decoder and sense amplifier with integrated latch

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
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Progamable control clock circuit for arrays

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
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Profile ID: LFUS-PAI-P-868731

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