Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2007-01-23
2007-01-23
Lam, David (Department: 2827)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S203000, C365S233100
Reexamination Certificate
active
11055802
ABSTRACT:
A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated memory cells. Timing sequences in the CAM system are controlled by a series of individually triggered one shot pulse generators. The one shot pulse generators control the timing of CAM system activities, for example the precharge of CAM subsystems, so that these activities are staggered in time. This timing approach improves power consumption and evaluation time within the CAM system. By distributing precharging activities in time throughout the CAM cycle, current peaking during the CAM cycle is reduced. The CAM system latches results in an output latch that is controlled by a one shot pulse generator.
REFERENCES:
patent: 4618968 (1986-10-01), Sibigtroth
patent: 4723224 (1988-02-01), Van Hulett et al.
patent: 5383146 (1995-01-01), Threewitt
patent: 6289414 (2001-09-01), Feldmeier et al.
patent: 6646900 (2003-11-01), Tsuda et al.
patent: 6738862 (2004-05-01), Ross et al.
patent: 6744688 (2004-06-01), Gillingham et al.
patent: 6775168 (2004-08-01), Park et al.
patent: 6839256 (2005-01-01), Proebsting et al.
patent: 2002/0032681 (2002-03-01), Feldmeier et al.
Arsovski et al., “A Ternary Content-Addressable Memory . . .”, IEEE Journal of Solid State Circuits, vol. 38, No. 1, (Jan. 2003).
Berkeley, “EE141 Lecture 19-Sequential Logic” (Fall 2004).
Crunch, “Exploring the Basics of AC Scan”. Inovys (c) Jul. 2004.
DEFOSSEZ, “XAPP202 Xilinx—CAM in ATM Applications” (Jan. 2001).
Helwig, et al., “High Speed CAM”, IBM Deutschland Entwicklung GmbH (1996).
Krishnamurthy, “Address Translation—Lecture Notes” (Spring 2004).
Krishnamurthy, “Address Translation (cont'd)—Lecture Notes” (Spring 2004).
Music Semiconductors, Application Note AN-N19, “Using The MU9C1965A LANCAM MP For Data Wider Than 128 Bits” (Sep. 1998).
Music Semiconductors, Prelim. Data Sheet—MU9C1965A/L LANCAM MP (Jul. 2002).
Music Semiconductors, Application Brief AB-N6—What is a CAM? (Sep. 1998).
PAGIAMTZIS, “Content—Adressable Memory Introduction” (c) 1993.
PAGIARRTZIS, “Low Power CAM Using Pipelined Hierarchical Search Scheme, IEEE Journal of Solid State Circuits”, (Sep. 2004).
PAGIAMTZIS, Pipelined Match-Lines and Hierarchical Search-Lines for Low Power CAMs, IEEE (Sep. 2003).
Stojanovic, et al., “Comp Analysis of MS Latches”, IEEE Journal of Solid-State Circuits, vol. 34, No. 4 (Apr. 1999).
Chan Yuen Hung
Khan Masood Ahmed
Lee Michael Ju Hyeok
Seewann Ed
International Business Machines - Corporation
Kahler Mark P.
Lam David
McBurney Mark E.
LandOfFree
Method and apparatus for controlling the timing of precharge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for controlling the timing of precharge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for controlling the timing of precharge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3731809