Multifunctional latch circuit for use with both SRAM array...

Details Multifunctional latch circuit for use with both SRAM array... Multifunctional latch circuit for use with both SRAM array...

2006-08-29

2006-08-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S185080, C365S230080

Reexamination Certificate

active

07099201

ABSTRACT:
An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

REFERENCES:
patent: 5751727 (1998-05-01), Martens
patent: 6930941 (2005-08-01), Nakase

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