4. Static information storage and retrieval
  5. Read only systems
  6. Semiconductive

Xavier Vera

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Clustered variations-aware architecture

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate

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Correcting intermittent errors in data storage structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Enhancing reliability of a many-core processor

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Memory content inverting to minimize NTBI effects

Static information storage and retrieval – Systems using particular element – Flip-flop
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NBTI-resilient memory cells with NAND gates

Static information storage and retrieval – Read only systems – Semiconductive
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Profile ID: LFUS-PAI-P-3165880

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