Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-02-28
2011-12-06
Beausoliel, Jr., Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000, C714S048000, C714S049000
Reexamination Certificate
active
08074110
ABSTRACT:
In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.
REFERENCES:
patent: 4191996 (1980-03-01), Chesley
patent: 4519035 (1985-05-01), Chamberlain
patent: 2002/0188877 (2002-12-01), Buch
patent: 2003/0067894 (2003-04-01), Schmidt
patent: 2003/0074598 (2003-04-01), Bossen et al.
patent: 2004/0037346 (2004-02-01), Rusu et al.
patent: 2004/0123201 (2004-06-01), Nguyen et al.
patent: 2004/0230865 (2004-11-01), Balazich et al.
patent: 2005/0044319 (2005-02-01), Olukotun
patent: 2005/0050373 (2005-03-01), Orenstien et al.
patent: 2005/0102565 (2005-05-01), Barr et al.
patent: 2006/0053326 (2006-03-01), Naveh et al.
patent: 2006/0212677 (2006-09-01), Fossum
patent: 2007/0074011 (2007-03-01), Borkar et al.
patent: 2007/0174746 (2007-07-01), Haefliger et al.
patent: 2008/0148269 (2008-06-01), Wong et al.
patent: 2009/0249094 (2009-10-01), Marshall et al.
patent: 2004-062470 (2004-02-01), None
patent: 200462470 (2004-02-01), None
patent: 2005-085164 (2005-03-01), None
patent: 200585164 (2005-03-01), None
patent: 2005-129053 (2005-05-01), None
patent: 2005129053 (2005-05-01), None
Brooks, “Dynamic Thermal Managment for High-Performance Microprocessors”, Jan. 2001, ISHPCA, p. 1-12.
Sharma, “Balance of Power: Dynamic Thermal Managment for Internet Data Centers”, Feb. 18, 2003, HP, p. 1-14.
Heo, “Reducing Power Density through Activity Migration”, Aug. 2003, ISLPED, p. 1-6.
Skadron, “Temperature-Aware Microarchitecure: Modeling and Implementation”, Mar. 2004, ACM, p. 94-125.
Chinese Patent Office, First Office Action mailed Oct. 23, 2009, in Chinese patent application No. 200680053450.0.
Japanese Patent Office, Notice of Reasons for Rejection dated Mar. 2, 2010, in Japanese patent application No. 2008-551806.
Kyriakos Stavrou, et al., “TSIC: Thermal Scheduling Simulator for Chip Multiprocessors,” 2005, pp. 589-599.
PCT/ES2006/070021 International Search Report with Written Opinion of the International Searching Authority Mailed Feb. 28, 2006 (in Spanish).
Pedro Chapparro, et al., “Thermal-Aware Clustered Microarchitectures,” 2004, pp. 1-6.
T. Simunic, et al., “Optimization of Reliability and Power Consumption in Systems on a Chip,” 2005, pp. 1-10.
Japanese Patent Office, Final Notice of Reasons for Rejection dated Jul. 13, 2010, in Japanese patent application No. 2008-551806.
Japan Patent Office, Office Action for JP Application No. 2008-551806 (with English translation), dated Jul. 13, 2010, 5 pgs.
Chinese Patent Office, Second Office Action mailed May 11, 2011 in Chinese application No. 200680053450.0.
Abella Jaume
Ergin Oguz
González Antonio
Unsal Osman
Vera Xavier
Arcos Jeison C
Beausoliel, Jr. Robert
Intel Corporation
Trop Pruner & Hu P.C.
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