NBTI-resilient memory cells with NAND gates

Details NBTI-resilient memory cells with NAND gates NBTI-resilient memory cells with NAND gates

2006-12-15

2008-11-04

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read only systems

Semiconductive

C365S072000, C365S154000

Reexamination Certificate

active

07447054

ABSTRACT:
An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience less degradation than in inverter-based memory cells. Guard-banding to account for transistor degradation may be mitigated, or the operating frequency of the memory cell may be increased.

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