Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S727000, C714S731000, C714S738000
Reexamination Certificate
active
07877715
ABSTRACT:
A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.
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Evmorfopoulos, N. et al., “Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification”; International Conference on Computer Aided Design, ICCAD'06; Nov. 5-9, 2006, San Jose, CA; pp. 112-118.
Bhabu Shaleen
Chickermane Vivek
Thirunavukarasu Senthil Arasu
Cadence Design Systems Inc.
Levin Naum B
Schwegman Lundberg & Woessner, P.A.
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