Uwe Kranich

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Apparatus and method for reducing read miss latency by predictin

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Apparatus and method for reducing the cache miss penalty in a vi

Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent

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Basic block oriented trace cache utilizing a basic block...

Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate

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Cache system and method for providing software controlled writeb

Patent

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Computer system employing a bus conversion bridge for interfacin

Boots – shoes – and leggings
Patent

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Profile ID: LFUS-PAI-P-615665

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