Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-06-05
1998-05-12
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711125, 395856, G06F 938
Patent
active
057522634
ABSTRACT:
An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any nonsequential instructions. The cache controller stores an indication of whether the line contains nonsequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any nonsequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.
REFERENCES:
patent: 4821185 (1989-04-01), Esposito
patent: 4860192 (1989-08-01), Sachs
patent: 4860199 (1989-08-01), Langendorf et al.
patent: 4882642 (1989-11-01), Tayler et al.
patent: 5235697 (1993-08-01), Steely, Jr. et al.
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5461718 (1995-10-01), Tatosian et al.
patent: 5473764 (1995-12-01), Chi
patent: 5483641 (1996-01-01), Jones et al.
patent: 5524220 (1996-06-01), Verma et al.
patent: 5553305 (1996-09-01), Gregor et al.
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5588128 (1996-12-01), Hicok et al.
Edmondson et al., "Superscaler Instruction Execution in the 21164 Alpha Microprocessor", IEEE Micro, vol. 15:33-43, (1995).
Undy et al., "A Low-Cost Graphics and Multimedia Workstation Chip Set", IEEE Micro, vol. 14:10-22, (1994).
Advanced Micro Devices , Inc.
Peikari J.
Swann Tod R.
LandOfFree
Apparatus and method for reducing read miss latency by predictin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for reducing read miss latency by predictin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for reducing read miss latency by predictin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-996745