Apparatus and method for reducing the cache miss penalty in a vi

Details Apparatus and method for reducing the cache miss penalty in a vi Apparatus and method for reducing the cache miss penalty in a vi

1997-09-03

1999-05-04

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711213, G06F 1208

Patent

active

059000228

ABSTRACT:
An apparatus and method for reducing the cache miss penalty in a virtual memory system is provided. The virtual memory system includes a processor core which generates virtual addresses and a cache configured to supply information in response to receipt of physical addresses. The apparatus includes a logical-to-physical translation unit which converts the virtual addresses generated by the processor core to physical addresses. The logical-to-physical translation unit includes an accurate translation unit, a speculative translation unit, and a comparing unit. The accurate translation unit accurately converts logical addresses to physical addresses. The speculative translation unit generates and transmits a speculative physical address to the cache before the accurate translation unit completes generation of the accurate physical address. When the accurate translation unit completes generation of the accurate physical address, the comparing unit compares the accurate physical address with the speculative physical address. If the accurate physical address does not match the speculative physical address, the transmission of the speculative physical address to the cache is aborted, and the accurate physical address is transmitted to the cache.

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