Todd Michael Austin

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Data retention latch provision within integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Error detection and recovery within processing stages of an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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Error recovery within processing stages of an integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate

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Memory system having fast and slow data reading mechanisms

Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate

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Memory system having fast and slow data reading mechanisms

Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate

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Profile ID: LFUS-PAI-P-832193

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