Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2009-08-21
2011-11-15
Baker, Stephen (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
08060814
ABSTRACT:
An integrated circuit includes a plurality of processing stages each including processing logic1014, a non-delayed signal-capture element1016, a delayed signal-capture element1018and a comparator1024. The non-delayed signal-capture element1016captures an output from the processing logic1014at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element1018also captures a value from the processing logic1014. An error detection circuit1026and error correction circuit1028detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator1024. The comparator1024compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
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Austin Todd Michael
Blaauw David Theodore
Das Shidhartha
ARM Limited
Baker Stephen
Nixon & Vanderhye P.C.
The Regents of the University of Michigan
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