Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-10-02
2007-10-02
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S010000, C714S819000
Reexamination Certificate
active
10392382
ABSTRACT:
An integrated circuit includes a plurality of processing stages each including processing logic2, a non-delayed latch4, a delayed latch8and a comparator6. The non-delayed latch4captures an output from the processing logic2at a non-delayed capture time. At a later delayed capture time, the delayed latch8also captures a value from the processing logic2. The comparator6compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a maimer that increases overall performance.
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Austin Todd Michael
Blaauw David Theodore
Flautner Krisztian
Mudge Trevor Nigel
ARM Limited
Britt Cynthia
Nixon & Vanderhye P.C.
University of Michigan
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