4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Mukul R. Prasad

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Estimating the difficulty level of a formal verification...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Generating a test sequence using a satisfiability technique

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Performing latch mapping of sequential circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Scheduling events in a boolean satisfiability (SAT) solver

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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System and method for verifying a digital design using...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Profile ID: LFUS-PAI-P-2930184

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