Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-20
2007-03-20
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10807959
ABSTRACT:
In one embodiment, a method for scheduling events in a Boolean satisfiability (SAT) solver includes collecting one or more first-order statistics on a search for a valid solution to an SAT problem, deriving one or more second-order statistics on the search from the one or more first-order statistics, and scheduling events in the search according to one or more of the second-order statistics.
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Mukherjee Rajarshi
Prasad Mukul R.
Baker & Botts L.L.P.
Lin Sun James
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