Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-18
2006-04-18
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07032192
ABSTRACT:
Performing latch mapping includes receiving an initial circuit model representing a first circuit and a second circuit and generating an initial latch mapping for the initial circuit model. The following is repeated until a next latch mapping is at least similar to a current latch mapping to yield a final latch mapping. A current circuit model is constructed according to a previous circuit model. Current potentially equivalent node sets associated with the current circuit model are established in accordance with previous potentially equivalent node sets, where each potentially equivalent node set includes potentially equivalent nodes. Equivalence of the current potentially equivalent node sets is validated, and a current latch mapping is verified in accordance with the validated current potentially equivalent node sets to generate a next latch mapping. The final latch mapping is reported.
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Jain Jawahar
Mukherjee Rajarshi
Ng Kelvin K. C.
Prasad Mukul R.
Baker & Botts L.L.P.
Fujitsu Limited
Garbowski Leigh M.
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