4. Static information storage and retrieval
  5. Read/write circuit

Michiru Hori

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Code synchronization decision circuit of Viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate

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FIFO memory device having address detection portion

Static information storage and retrieval – Read/write circuit
Patent

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Trellis decoder

Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate

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Viterbi decoder and synchronism controlling method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1630510

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