Trellis decoder

Details Trellis decoder Trellis decoder

1999-01-14

2002-05-14

Pham, Chi (Department: 2731)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C714S795000

Reexamination Certificate

active

06389083

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a Trellis decoder in a trellis coding modulation system, and more particularly to a Trellis decoder used especially in a QAM modulation/demodulation system for concurrently changing the amplitude and the phase.
BACKGROUND OF THE INVENTION
In a multilevel QAM modulation/demodulation system, an error may occur in a signal after the QAM demodulation due to noise or reflection generated in a transmission path during signal transmission. Therefore, a transmission signal is subjected to coding for error correction for transmission at a transmitting side.
As for a multilevel QAM symbol in the multilevel QAM modulation/demodulation system, each symbol in the I axis and Q axis is expressed with an X bit such as “Ix−1 Ix−2 . . . Ix−1 Ix0, Qx−1 Qx−2 . . . Qx1 Qx0” (any of “Ix−1”, “Ix−2”, “Ix1”, “Ix0”, “Qx−1”, “Qx−2”, “Qx1” and “Qx0” is either “0” or “1”). The transmitting side of the multilevel QAM modulation/demodulation system subjects a signal to multilevel QAM modulation and transmits the modulated signals by allocating data subjected to convolutional coding to “Ix0” and “Qx0” both of which are the least significant bits (described LSB hereinafter) in the multilevel QAM symbols and also allocating data not being subjected to convolutional coding to a part of high-order “X−1” bits in the “Ix−1” to “Ix1” bits and in the “Qx−1” to “Qx1” bits excluding the LSBs in the symbols in the I axis and Q axis.
A receiving side subjects a received signal to multilevel QAM demodulation to obtain a demodulated signal, inputs the signal into a Trellis decoder and corrects an error therefor, and estimates a QAM symbol transmitted at the transmitting side. The demodulated signal in the I axis and Q axis is an N-bit soft decision signal respectively. A part of the high-order “X” bits in the signal represents an estimated value of the QAM symbol, and a part of the low-order “N−X” bit excluding the part of high-order “X” bit represents an error from each of the QAM symbols in the I axis and Q axis respectively.
The Trellis decoder generally comprises a delay circuit of a Viterbi decoder, an area determining circuit or a RAM; a selection circuit; a convolutional coder; and a demapper. Error correction for each “N−X+1” bit in a demodulated signal corresponding to the LSB in each of the QAM symbols in the I axis and Q axis is executed in the Viterbi decoder. Error correction for a part of a high-order “X−1” bit in each of the QAM symbols is executed by using each estimated value of the LSB in each of the QAM symbols obtained by re-coding a result of error correction with the Viterbi decoder by the convolutional coder. A sign of each part of the high-order “X−1” bit in each of the QAM symbols is delayed in the delay circuit and inputted into the selection circuit. With the operation, phases between signs of the parts of high-order “X−1” bits in the QAM symbols and estimated values of the LSBs in the QAM symbols are correlated in the selection circuit.
FIG. 8
is a simulated view showing a correlation between 64QAM modulated signals and QAM symbols in the I axis for explaining conventional type of error correction for QAM symbols. In
FIG. 8
, 64QAM symbols are expressed with “I2 I1 I0”, and demodulated signals Ir in the I axis are expressed with “Ir2 Ir1 Ir0 Ie3 Ie2 Ie1 Ie0”, which are expressed with complement numbers of two. A correlation between 64QAM modulated signals and QAM symbols in the Q axis is the same as described above. It is assumed that, when the transmitting side sends a symbol A “110” (mark ♦ in
FIG. 8
) and the receiving side demodulates the symbol, an error occurs in the demodulated signal due to noise in the transmission path so that a demodulated signal B “101xxxx” (mark × in
FIG. 8
) or a demodulated signal C “111xxxx” (mark +in
FIG. 8
) are obtained. The mark x in the signals represents either “0” or “1”.
(1) Error Correction for Demodulated Signal B “101xxxx”
Even if a value obtained by re-coding a result of error correction by the Viterbi decoder with the convolutional coder is “0”, the high-order two bits in the demodulated signal are still “10”, and hence, the demodulated signal can not be corrected to the transmitted symbol A “110”. Therefore, when a demodulated signal is the demodulated signal B, the area determining circuit needs to output four bits of “10” and “11” in case where the LSBs in the QAM symbols are “1” and “0”. The selection circuit corrects, when the LSB at the symbol point is “0”, an error for the high-order two bits in the demodulated signal by selecting output “11” from the area determining circuit.
(2) Error Correction for Demodulated Signal C “111xxxx”
Even if a value obtained by re-coding a result of error correction by the Viterbi decoder with the convolutional coder is either “0” or “1”, the high-order two bits in the demodulated signal are still “11”. Therefore, when a demodulated signal is the demodulated signal C, the area determining circuit needs to output four bits of “11” and “11” in case where the LSBs in the QAM symbols are “1” and “0”.
Description below provides a summary of results of output from the area determining circuit and selection circuit based on the conventional technology.
(1) When a demodulated signal is in a range from “1000000” to “1010111” (Area (
1
) in FIG.
8
), the area determining circuit outputs “10” and “10”, and the selection circuit outputs “10” and “10” when the LSBs therein are “0” and “1” respectively.
(2) When a demodulated signal is in a range from “1011000” to “1100111” (Area (
2
) in FIG.
8
), the area determining circuit outputs “11” and “10”, and the selection circuit outputs “11” and “10” when the LSBs therein are “0” and “1” respectively.
(3) When a demodulated signal is in a range from “1101000” to “1110111” (Area (
3
) in FIG.
8
), the area determining circuit outputs “11” and “11”, and the selection circuit outputs “11” and “11” when the LSBs therein are “0” and “1” respectively.
(4) When a demodulated signal is in a range from “1111000” to “1111111” and from “0000000” to “0000111” (Area (
4
) in FIG.
8
), the area determining circuit outputs “00” and “11”, and the selection circuit outputs “00” and “11” when the LSBs therein are “0” and “1” respectively.
(5) When a demodulated signal is in a range from “0001000” to “0010111” (Area (
5
) in FIG.
8
), the area determining circuit outputs “00” and “00”, and the selection circuit outputs “00” and “00” when the LSBs therein are “0” and “1” respectively.
(6) When a demodulated signal is in a range from “0011000” to “0100111” (Area (
6
) in FIG.
8
), the area determining circuit outputs “00” and “00”, and the selection circuit outputs “01” and “00” when the LSBs therein are “0” and “1” respectively.
(7) When a demodulated signal is in a range from “0101000” to “0111111” (Area (
7
) in FIG.
8
), the area determining circuit outputs “01” and “01”, and the selection circuit outputs “01” and “01” when the LSBs therein are “0” and “1” respectively.
In the conventional type of Trellis decoder, however, when an error is to be corrected for a part of a high-order “X−1” bit in a QAM symbol, “(X−1)×4” bits in I and Q axis respectively, total “(X−1)×2” bits, are required as an output from the area determining circuit.
Therefore, a size of a delay circuit of a RAM or the like into which output from the area determining circuit is inputted is “(X−1)×4 bits×m”. Herein m indicates a delay after a value at the “N−X+1” bit from the high order bit in the demodulated signal is inputted into a Trellis decoder until the value is re-coded. For example, in a case of 64QAM, the area determining circuit outputs a 4-bit sign for each of the axes as described above, so that a 8-bit sign as a total of the signs in the Q axis and I axis will be inputted into the delay circuit. Therefore, conventionally, a scale of a delay circuit has been “8 bits&tim

Affiliated with

Also associated with

Rating

Trellis decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trellis decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trellis decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2841866